參數(shù)資料
型號(hào)： ISL6112INZA-T
廠商： Intersil
文件頁(yè)數(shù)： 19/30頁(yè)
文件大?。?/td> 938K
描述： IC PWR CNTRLR DUAL SLT 48-TQFP
標(biāo)準(zhǔn)包裝： 1,000
類型： 熱交換控制器
應(yīng)用： 通用型，PCI Express?
內(nèi)部開(kāi)關(guān)： 無(wú)
電源電壓： 3.3V，12V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 帶卷 (TR)
ISL6112
19
FN6456.1
August 25, 2011
Start bit must then be sent to the ISL6112, followed by a repeat
of the device address, with the R/W
 bit set to the high (read)
state. The data to be read from the part may then be clocked out.
The exception to this rule is that, if the location latched in the
pointer register from the last write operation is known to be
correct (i.e., points to the desired register within the ISL6112),
the Receive_Byte procedure may be used. To perform a
Receive_Byte operation, the host sends an address byte to select
the target ISL6112, with the R/W
 bit set to the high (read) state,
and then retrieves the data byte. Figures 33, 34 and 35 show the
formats for these data read and data write procedures.
The Command Register is eight bits (one byte) wide. This byte
carries the address of the ISL6112 register to be operated upon.
Command byte values corresponding to the ISL6112 register
addresses are shown in Table 4. Command byte values other than
0000 0XXX
b
 = 00
h
  07
h
 
are reserved and should not be used.
ISL6112 SMBus Address Configuration
The ISL6112 responds to its own unique SMBus address, which
is assigned using A2, A1, and A0. These represent the three
Least Significant Bits (LSB) of its 7-bit address, as shown in
Table3. These address bits are assigned only during power-up of
the VSTBY supply input. These address bits allow up to eight
ISL6112 devices in a single system. These pins are either
grounded or left unconnected to specify a logical 0 or logical 1,
respectively. A pin designated as a logical 1 may also be pulled
up to VSTBY.
TABLE 3. ISL6112 SMBUS ADDRESSING
INPUTS
ISL6112 DEVICE ADDRESS
A2
A1
A0
BINARY
HEX
0
0
0    1000 000X*b
80h
0
0
1    1000 001Xb
82h
0
1
0    1000 010Xb
84h
0
1
1    1000 011Xb
86h
1
0
0    1000 100Xb
88h
1
0
1    1000 101Xb
8Ah
1
1
0    1000 110Xb
8Ch
1
1
1    1000 111Xb
8Eh
* Where X = 1 for READ and 0 for WRITE
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