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參數(shù)資料
| 型號： | IS42S16128-12T |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 256K X 16 SYNCHRONOUS DRAM, 12 ns, PDSO50 |
| 封裝： | 0.400 INCH, TSOP2-50 |
| 文件頁數(shù)： | 31/75頁 |
| 文件大?。?/td> | 638K |
| 代理商： | IS42S16128-12T |
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IS42S16128
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00
31
Write Cycle (Full Page) Interruption
Using the Burst Stop Command
The IS42S16128 can input data continuously from the
burst start address (a) to location a+255 during a write
cycle in which the burst length is set to full page. The
IS42S16128 repeats the operation starting at the 256th
cycle with data input returning to location (a) and continu-
ing with a+1, a+2, a+3, etc. A burst stop command must
be executed to terminate this cycle. A precharge com-
mand must be executed within the ACT to PRE command
period (t
RAS
max.) following the burst stop command.
After the period (t
WBD
) required for burst data input to stop
following the execution of the burst stop command has
elapsed, the write cycle terminates. This period (t
WBD
) is
zero clock cycles, regardless of the
CAS
latency.
CAS
latency = 2, 3, burst length = full page
Burst Data Interruption Using the
U/LDQM Pins (Read Cycle)
Burst data output can be temporarily interrupted (masked)
during a read cycle using the U/LDQM pins. Regardless
of the
CAS
latency, two clock cycles (t
QMD
) after one of the
U/LDQM pins goes HIGH, the corresponding outputs go
to the HIGH impedance state. Subsequently, the outputs
are maintained in the high impedance state as long as
that U/LDQM pin remains HIGH. When the U/LDQM pin
goes LOW, output is resumed at a time t
QMD
later. This
output control operates independently on a byte basis
with the UDQM pin controlling upper byte output (pins
I/O8-I/O15) and the LDQM pin controlling lower byte
output (pins I/O0 to I/O7).
Since the U/LDQM pins control the device output buffers
only, the read cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
CAS
latency = 2, burst length = 4
WRITE A0
COMMAND
I/O
CLK
D
IN
A0
D
IN
A1
D
IN
A
D
IN
A1
D
IN
A2
t
WBD=0
t
RP
READ (CA=A, BANK 0)
BURST STOP
BST
PRE 0
INVALID DATA
PRECHARGE (BANK 0)
READ A0
COMMAND
UDQM
LDQM
I/O8-I/O15
I/O0-I/O 7
CLK
D
OUT
A0
t
QMD=2
HI-Z
HI-Z
HI-Z
READ (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
D
OUT
A2
D
OUT
A3
D
OUT
A1
D
OUT
A0
Don
’
t Care
相關PDF資料 |
PDF描述 |
|---|---|
| IS42S16128-8T | Chassis Mount and Din Rail Filters RoHS Compliant: Yes |
| IS42S16160B-7TL | 32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM |
| IS42S16160B-7TLI | 32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM |
| IS42S83200B | 32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM |
| IS42S83200B-6T | 32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IS42S16128-8T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16160A-6T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256 Mb Synchronous DRAM |
| IS42S16160A-6TL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256 Mb Synchronous DRAM |
| IS42S16160A-7T | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS42S16160A-7TL | 制造商:Integrated Silicon Solution Inc 功能描述: |
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