參數(shù)資料
型號(hào): IS42S16128-12T
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 256K X 16 SYNCHRONOUS DRAM, 12 ns, PDSO50
封裝: 0.400 INCH, TSOP2-50
文件頁數(shù): 30/75頁
文件大小: 638K
代理商: IS42S16128-12T
30
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00
IS42S16128
ISSI
Read Cycle (Full Page) Interruption Using
the Burst Stop Command
The IS42S16128 can output data continuously from the
burst start address (a) to location a+255 during a read
cycle in which the burst length is set to full page. The
IS42S16128 repeats the operation starting at the 256th
cycle with the data output returning to location (a) and
continuing with a+1, a+2, a+3, etc. A burst stop command
must be executed to terminate this cycle. A precharge
command must be executed within the ACT to PRE
command period (t
RAS
max.) following the burst stop
command.
After the period (t
RBD
) required for burst data output to
stop following the execution of the burst stop command
has elapsed, the outputs go to the HIGH impedance state.
This period (t
RBD
) is one clock cycle when the
CAS
latency
is one, two clock cycle when the
CAS
latency is two and
three clock cycle when the CAS latency is three.
CAS
Latency
3
2
t
RBD
3
2
COMMAND
I/O
CLK
t
RBD
BST
READ A0
COMMAND
I/O
CLK
t
RBD
READ (CA=A, BANK 0)
BURST STOP
READ A0
READ (CA=A, BANK 0)
BURST STOP
BST
HI-Z
HI-Z
D
OUT
A0
D
OUT
A0
D
OUT
A0
D
OUT
A0
D
OUT
A1
D
OUT
A1
D
OUT
A2
D
OUT
A2
D
OUT
A3
D
OUT
A3
CAS
latency = 2, burst length = full page
CAS
latency = 3, burst length = full page
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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