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參數(shù)資料
| 型號： | IRU3073CQTR |
| 廠商： | International Rectifier |
| 文件頁數(shù)： | 13/21頁 |
| 文件大小： | 236K |
| 描述： | IC REG DL BCK/LINEAR 16-QSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 拓?fù)洌?/td> | 降壓（降壓）同步（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 2 |
| 頻率 - 開關(guān)： | 210kHz ~ 400kHz |
| 電壓/電流 - 輸出 1： | 控制器 |
| 電壓/電流 - 輸出 2： | 0.8 V ~ 22.5 V，65mA |
| 帶 LED 驅(qū)動器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 是 |
| 電源電壓： | 4.4 V ~ 25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | *IRU3073CQTR IRU3073CQCT |
IRU3073
13
Rev. 1.0
09/17/03
www.irf.com
LDO Section
Output Voltage Programming
Output voltage for LDO is programmed by reference volt-
age and external voltage divider. The Fb2 pin is the in-
verting input of the error amplifier, which is internally ref-
erenced to 0.8V. The divider is ratioed to provide 0.8V at
the Fb2 pin when the output is at its desired value. The
output voltage is defined by using the following equation
Results to R7=1KV
Figure 13 - Programming the output voltage for LDO.
LDO Power MOSFET Selection
The first step in selecting the power MOSFET for the
linear regulator is to select the maximum RDS(ON) based
on the input to the dropout voltage and the maximum
load current.
Results to: RDS(ON)(MAX) = 0.45V
Note that since the MOSFET RDS(ON) increases with tem-
perature, this number must be divided by ~1.5 in order
to find the RDS(ON)(MAX) at room temperature. The IRLR2703
has a maximum of 0.065V RDS(ON) at room temperature,
which meets our requirements.
R7
R10
VOUT2 = VREF3 1+
( )
For:
VOUT2 = 1.6V
VREF = 0.8V
R10 = 1KV
Layout Consideration
The layout is very important when designing high fre-
quency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
Start to place the power components. Make all the con-
nections in the top layer with wide, copper filled areas.
The inductor, output capacitor and the MOSFET should
be close to each other as possible. This helps to reduce
the EMI radiated by the power traces due to the high
switching currents through them. Place input capacitor
directly to the drain of the high-side MOSFET. To reduce
the ESR, replace the single input capacitor with two par-
allel units. The feedback part of the system should be
kept away from the inductor and other noise sources
and be placed close to the IC. In multilayer PCB, use
one layer as power ground plane and have a separate
control circuit ground (analog ground), to which all sig-
nals are referenced. The goal is to localize the high cur-
rent path to a separate loop that does not interfere with
the more sensitive analog control function. These two
grounds must be connected together on the PC board
layout at a single point.
Figure 14 - Switching Frequency vs. Rt.
0
50
100
150
200
250
300
350
400
450
500
0
50
100 150 200 250
300 350 400 450 500 550
Rt (KV)
Fb2
IRU3073
VOUT2
R10
R7
RDS(ON) =
VIN(LDO) - VOUT2
IOUT2
For:
VIN(LDO) = 2.5V
VOUT2 = 1.6V
IOUT2 = 2A
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