參數(shù)資料
型號: IRLR8503PBF
廠商: International Rectifier
英文描述: HEXFET Power MOSFET
中文描述: HEXFET功率MOSFET
文件頁數(shù): 3/8頁
文件大小: 244K
代理商: IRLR8503PBF
www.irf.com
3
IRLR8503PbF
Device Capacitance
Corresponding Charge Parameter
C
GS
Q
GS
Q
G
Q
GD
C
GS
+ C
GD
C
GD
Power MOSFET Optimization for DC-DC Converters
While the IRLR8103V and IRLR8503 can and are be-
ing used in a variety of applications, they were designed
and optimized for low voltage DC-DC conversion in a
synchronous buck converter topology, specifically, mi-
croprocessor power applications. The IRLR8503 (Fig-
ure 1) was optimized for the control FET socket, while
the IRLR8103V was optimized for the synchronous
FET function.
Because of the inter-electrode capacitance (Figure 2)
of the Power MOSFET, specifying the R
of the de-
vice is not enough to ensure good performance. An
optimization between R
and charge must be per-
formed to insure the best performing MOSFET for a
given application. Both die size and device architec-
ture must be varied to achieve the minimum possible
in-circuit losses. This is independently true for both
control FET and synchronous FET. Unfortunately, the
capacitances of a FET are non-linear and voltage de-
pendent. Therefore, it is inconvenient to specify and
use them effectively in switching power supply power
loss estimations. This was well understood years ago
and resulted in changing the emphasis from capaci-
tance to gate charge on Power MOSFET data sheets.
International Rectifier has recently taken the industry
a step further by specifying new charge parameters
that are even more specific to DC-DC converter de-
sign (Table 2). In order to understand these parameters,
it is best to start with the in-circuit waveforms in Fig-
ure 3 & Figure 4.
Figure 1 – Application
Topology
Figure 2 – Inter-electrode
Capacitance
Table 1 – Traditional Charge Parameters
Table 2 – New Charge Parameters
Figure 3 – Control FET
Waveform
The waveforms are broken into segments correspond-
ing to charge parameters. These, in turn, correspond
to discrete time segments of the switching waveform.
Figure 4 – Sync FET
Waveform
New Charge
Parameter
Description
Waveform
Q
GS1
Q
GS2
Q
GCONT
Q
SWITCH
Pre-Threshold Gate Charge
Post-Threshold Gate Charge
Figure 3
Control FET Total Q
G
Charge during control FET switching
Combines Q
GS2
and Q
GD
Output charge
Charge supplied to C
during the Q
GD
period of control FET switching
Q
OSS
Figure 5
Figure 6
Q
GSYNC
Synchronous FET Total Q
G
(V
DS
0)
Figure 4
Losses may be broken into four categories: conduc-
tion loss, gate drive loss, switching loss, and output
loss. The following simplified power loss equation is
true for both MOSFETs in a synchronous buck con-
verter:
For the synchronous FET, the P
SWITCH
term becomes
virtually zero and is ignored.
P
LOSS
= P
CONDUCTION
+ P
GATE DRIVE
+ P
SWITCH
+ P
OUTPUT
Figure 5 – Q
Equivalent Circuit
Figure 6 – Q
OSS
Waveforms
Coss1
2n
RLR8503
(Cont FET)
IRLR8103V
(Sync FET)
CGD
CGS
CDS
Drain Voltage
Gate Voltage
Drain Current
QGD
Q
Q
VGTH
QSwitch
(ConQG
Drain Voltage
0 V
Gate Voltage
VGTH
0 A
Drain Current
Time
Body
QG (Sync FET)
g1
g2
N1
N2
SN
Coss2
2n
VIN
Switch node voltage
(VSN)
N1 Gate
Voltage
N1 Current
N1 Coss Discharge
+
N2 Coss Charge
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