
Embedded Write-Back Enhanced IntelDX4 Processor
23
WB/WT#
I
The
Write-Back/Write-Through
pin enables Enhanced Bus mode (write-back
cache). It also defines a cached line as write-through or write-back. For cache
configuration, WB/WT# must be valid during RESET and be active for at least two
clocks before and two clocks after RESET is de-asserted. To define write-back or
write-through configuration of a line, WB/WT# is sampled in the same clock as the
first RDY# or BRDY# is returned during a line fill (allocation) cycle.
CLKMUL, VCC5, AND VOLDET
CLKMUL
I
The
Clock Multiplier
input, defined during device RESET, defines the ratio of
internal core frequency to external bus frequency. If sampled low, the core
frequency operates at twice the external bus frequency (speed doubled mode). If
driven high, speed triple mode is selected. CLKMUL has an internal pull-up speed
to V
CC
. A 10-K
pullup resistor is recommended when the pin is tied high.
V
CC5
I
The
5V reference voltage
input is the reference voltage for the 5V-tolerant I/O
buffers. This signal should be connected to +5V ±5% for use with 5V logic. If all
inputs are from 3V logic, this pin should be connected to 3.3V.
VOLDET
O
A
Voltage Detect
signal allows external system logic to distinguish between a 5V
Intel486 processor and the 3.3V IntelDX4 processor. This signal is active LOW for
a 3.3V IntelDX4 processor. This pin is available only on the PGA version of the
Embedded Write-Back Enhanced IntelDX4 processor.
RESERVED PINS
RESERVED#
I
Reserved
is reserved for future use. This pin MUST be connected to an external
pull-up resistor circuit. The recommended resistor value is 10 kOhms. The pull-up
resistor must be connected only to the RESERVED# pin.
Do not share this
resistor with other pins requiring pull-ups.
Table 8.
Embedded Write-Back Enhanced IntelDX4 Processor Pin Descriptions
(Sheet 8 of 8)
Symbol
Type
Name and Function