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| 型號(hào)： | INTELDX4 |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded Write-Back Enhanced Processor(32位回復(fù)嵌入式增強(qiáng)型處理器) |
| 中文描述： | 嵌入式回寫增強(qiáng)型處理器（32位回復(fù)嵌入式增強(qiáng)型處理器） |
| 文件頁數(shù)： | 26/50頁 |
| 文件大?。?/td> | 534K |
| 代理商： | INTELDX4 |
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Embedded Write-Back Enhanced IntelDX4 Processor
22
IGNNE#
I
When the
Ignore Numeric Error
pin is asserted the processor will ignore a
numeric error and continue executing non-control floating point instructions, but
FERR# will still be activated by the processor. When IGNNE# is de-asserted the
processor will freeze on a non-control floating point instruction, if a previous
floating point instruction caused an error. IGNNE# has no effect when the NE bit in
control register 0 is set. IGNNE# is active LOW and is provided with a small
internal pull-up resistor. IGNNE# is asynchronous but setup and hold times t
20
and
t
21
must be met to ensure recognition on any specific clock.
WRITE-BACK ENHANCED MODE
CACHE#
O
The
CACHE#
output indicates internal cacheability on read cycles and burst write-
back on write cycles. CACHE# is asserted for cacheable reads, cacheable code
fetches and write-backs. It is driven inactive for non-cacheable reads, I/O cycles,
special cycles, and write-through cycles.
FLUSH#
I
Cache FLUSH#
is an existing pin that operates differently if the processor is
configured as Enhanced Bus mode (write-back). FLUSH# causes the processor to
write back all modified lines and flush (invalidate) the cache. FLUSH# is
asynchronous, but must meet setup and hold times t
20
and t
21
for recognition in any
specific clock.
HITM#
O
The
Hit/Miss to a Modified Line
pin is a cache coherency protocol pin that is
driven only in Enhanced Bus mode. When a snoop cycle is run, HITM# indicates
that the processor contains the snooped line and that the line has been modified.
Assertion of HITM# implies that the line will be written back in its entirety, unless
the processor is already in the process of doing a replacement write-back of the
same line.
INV
I
The
Invalidation Request
pin is a cache coherency protocol pin that is used only
in the Enhanced Bus mode. It is sampled by the processor on EADS#-driven
snoop cycles. It is necessary to assert this pin to get the effect of the processor
invalidate cycle on write-through-only lines
.
INV also invalidates the write-back
lines. However, if the snooped line is modified, the line will be written back and
then invalidated. INV must satisfy setup and hold times t
12
and t
13
for proper
operation.
PLOCK#
O
In the Enhanced bus mode,
Pseudo-Lock Output
is always driven inactive. In this
mode, a 64-bit data read (caused by an FP operand access or a segment
descriptor read) is treated as a multiple cycle read request, which may be a burst
or a non-burst access based on whether BRDY# or RDY# is returned by the
system. Because only write-back cycles (caused by snoop write-back or
replacement write-back) are write burstable, a 64-bit write will be driven out as two
non-burst bus cycles. BLAST# is asserted during both writes.
SRESET
I
For the Embedded Write-Back Enhanced IntelDX4 processor,
Soft RESET
operates similar to other the Intel486 processors. On SRESET, the internal
SMRAM base register retains its previous value, does not flush, write-back or
disable the internal cache. Because SRESET is treated as an interrupt, it is
possible to have a bus cycle while SRESET is asserted. SRESET is serviced only
on an instruction boundary. SRESET is asynchronous but must meet setup and
hold times t
20
and t
21
for recognition in any specific clock.
Table 8.
Embedded Write-Back Enhanced IntelDX4 Processor Pin Descriptions
(Sheet 7 of 8)
Symbol
Type
Name and Function
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