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參數(shù)資料
| 型號： | INTELDX4 |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded Write-Back Enhanced Processor(32位回復(fù)嵌入式增強(qiáng)型處理器) |
| 中文描述： | 嵌入式回寫增強(qiáng)型處理器（32位回復(fù)嵌入式增強(qiáng)型處理器） |
| 文件頁數(shù)： | 23/50頁 |
| 文件大?。?/td> | 534K |
| 代理商： | INTELDX4 |
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Embedded Write-Back Enhanced IntelDX4 Processor
19
SRESET
I
Soft Reset
pin duplicates all functionality of the RESET pin except that the
SMBASE register retains its previous value. For soft resets, SRESET must remain
active for at least 15 CLK periods. SRESET is active HIGH. SRESET is
asynchronous but must meet setup and hold times t
20
and t
21
for recognition in any
specific clock.
System Management Interrupt
input invokes System Management Mode (SMM).
SMI# is a falling-edge triggered signal which forces the Embedded Write-Back
Enhanced IntelDX4 processorinto SMM at the completion of the current instruction.
SMI# is recognized on an instruction boundary and at each iteration for repeat
string instructions. SMI# does not break LOCKed bus cycles and cannot interrupt a
currently executing SMM. The Embedded Write-Back Enhanced IntelDX4 proces-
sorlatches the falling edge of one pending SMI# signal while it is executing an
existing SMI#. The nested SMI# is not recognized until after the execution of a
Resume (RSM) instruction.
System Management Interrupt Active
, an active LOW output, indicates that the
Embedded Write-Back Enhanced IntelDX4 processoris operating in SMM. It is
asserted when the processor begins to execute the SMI# state save sequence and
remains active LOW until the processor executes the last state restore cycle out of
SMRAM.
Stop Clock Request
input signal indicates a request was made to turn off or
change the CLK input frequency. When the Embedded Write-Back Enhanced
IntelDX4 processorrecognizes a STPCLK#, it stops execution on the next
instruction boundary (unless superseded by a higher priority interrupt), empties all
internal pipelines and write buffers, and generates a Stop Grant bus cycle.
STPCLK# is active LOW. STPCLK# must be pulled high via a 10-KW pullup
resistor.
STPCLK# is an asynchronous signal, but must remain active until
the Embedded Write-Back Enhanced IntelDX4 processor issues the Stop
Grant bus cycle. STPCLK# may be de-asserted at any time after the
processor has issued the Stop Grant bus cycle.
SMI#
I
SMIACT#
O
STPCLK#
I
BUS ARBITRATION
BREQ
O
Bus Request
signal indicates that the Embedded Write-Back Enhanced IntelDX4
processorhas internally generated a bus request. BREQ is generated whether or
not the processor is driving the bus. BREQ is active HIGH and is never floated.
Bus Hold Request
allows another bus master complete control of the Embedded
Write-Back Enhanced IntelDX4 processorbus. In response to HOLD going active,
the processor floats most of its output and input/output pins. HLDA is asserted after
completing the current bus cycle, burst cycle or sequence of locked cycles. The
Embedded Write-Back Enhanced IntelDX4 processorremains in this state until
HOLD is de-asserted. HOLD is active HIGH and is not provided with an internal
pull-down resistor. HOLD must satisfy setup and hold times t
18
and t
19
for proper
operation.
Hold Acknowledge
goes active in response to a hold request presented on the
HOLD pin. HLDA indicates that the Embedded Write-Back Enhanced IntelDX4
processor has given the bus to another local bus master. HLDA is driven active in
the same clock that the processor floats its bus. HLDA is driven inactive when
leaving bus hold. HLDA is active HIGH and remains driven during bus hold.
HOLD
I
HLDA
O
Table 8.
Embedded Write-Back Enhanced IntelDX4 Processor Pin Descriptions
(Sheet 4 of 8)
Symbol
Type
Name and Function
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