參數(shù)資料
型號(hào)： INTEL387DX
英文描述： Intel387 DX - MATH COPROCESSOR
中文描述： Intel387霉素-數(shù)學(xué)協(xié)處理器
文件頁(yè)數(shù)： 27/41頁(yè)
文件大?。?/td> 435K
代理商： INTEL387DX
Intel387
TM
DX MATH COPROCESSOR
240448–10
Cycles 1 & 2 represent part of the operand transfer cycle for instructions involving either 4-byte or 8-byte operand loads.
Cycles 3 & 4 represent part of the operand transfer cycle for a store operation.
*
Cycles 1 & 2 could repeat here or T
I
states for various non-operand transfer cycles and overhead.
Figure 3.5. Nonpipelined Read and Write Cycles
3.4.2 PIPELINED BUS CYCLES
Because all the activities of the Intel387 DX MCP
bus interface occur either during the T
RS
state or
during the transitions to or from that state, the only
difference between a pipelined and a nonpipelined
cycle is the manner of changing from one state to
another. The exact activities in each state are de-
tailed in the previous section ‘‘Nonpipelined Bus Cy-
cles’’.
When the Intel386 DX CPU asserts ADS
Y
before
the end of a bus cycle, both ADS
Y
and READY
Y
are active during a T
RS
state. This condition causes
the MCP to change to a different state named T
P
.
The MCP activities in the transition from a T
RS
state
to a T
P
state are exactly the same as those in the
transition from a T
RS
state to a T
I
state in nonpipe-
lined cycles.
T
P
state is metastable; therefore, one clock period
later the MCP returns to T
RS
state. In consecutive
pipelined cycles, the MCP bus logic uses only T
RS
and T
P
states.
Figure 3.6 shows the fastest transition into and out
of the pipelined bus cycles. Cycle 1 in this figure
represents a nonpipelined cycle. (Nonpipelined write
cycles with only one T
RS
state (i.e. no wait states)
are always followed by another nonpipelined cycle,
because READY
Y
is asserted before the earliest
possible assertion of ADS
Y
for the next cycle.)
Figure 3.7 shows the pipelined write and read cycles
with one additional T
RS
states beyond the minimum
required. To delay the assertion of READY
Y
re-
quires external logic.
27
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