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參數(shù)資料
| 型號： | INTEL387DX |
| 英文描述： | Intel387 DX - MATH COPROCESSOR |
| 中文描述： | Intel387霉素-數(shù)學(xué)協(xié)處理器 |
| 文件頁數(shù)： | 23/41頁 |
| 文件大?。?/td> | 435K |
| 代理商： | INTEL387DX |
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Intel387
TM
DX MATH COPROCESSOR
3.2.1 BUS CONTROL LOGIC
The BCL communicates solely with the CPU using
I/O bus cycles. The BCL appears to the CPU as a
special peripheral device. It is special in two re-
spects: the CPU initiates I/O automatically when it
encounters ESC instructions, and the CPU uses re-
served I/O addresses to communicate with the BCL.
The BCL does not communicate directly with memo-
ry. The CPU performs all memory access, transfer-
ring input operands from memory to the MCP and
transferring outputs from the MCP to memory.
3.2.2 DATA INTERFACE AND CONTROL UNIT
The data interface and control unit latches the data
and, subject to BCL control, directs the data to the
FIFO or the instruction decoder. The instruction de-
coder decodes the ESC instructions sent to it by the
CPU and generates controls that direct the data flow
in the FIFO. It also triggers the microinstruction se-
quencer that controls execution of each instruction.
If the ESC instruction is FINIT, FCLEX, FSTSW,
FSTSW AX, or FSTCW, the control executes it inde-
pendently of the FPU and the sequencer. The data
interface and control unit is the one that generates
the BUSY
Y
, PEREQ and ERROR
Y
signals that syn-
chronize Intel387 DX MCP activities with the In-
tel386 DX CPU. It also supports the FPU in all opera-
tions that it cannot perform alone (e.g. exceptions
handling, transcendental operations, etc.).
3.2.3 FLOATING POINT UNIT
The FPU executes all instructions that involve the
register stack, including arithmetic, logical, transcen-
dental, constant, and data transfer instructions. The
data path in the FPU is 84 bits wide (68 significant
bits, 15 exponent bits, and a sign bit) which allows
internal operand transfers to be performed at very
high speeds.
3.3 System Configuration
As an extension to the Intel386 DX Microprocessor,
the Intel387 DX Math Coprocessor can be connect-
ed to the CPU as shown by Figure 3.3. A dedicated
240448–8
Figure 3.3. Intel386
TM
DX Microprocessor and Intel387
TM
DX Math Coprocessor System Configuration
23
23
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