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參數(shù)資料
| 型號： | Intel387 dx |
| 廠商： | Intel Corp. |
| 英文描述： | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
| 中文描述： | 霉素數(shù)學(xué)協(xié)處理器（32位數(shù)學(xué)協(xié)處理器） |
| 文件頁數(shù)： | 25/41頁 |
| 文件大?。?/td> | 406K |
| 代理商： | INTEL387 DX |
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Intel387
TM
DX MATH COPROCESSOR
Once it has started to execute a numerics instruction
and has transferred the operands from the Intel386
DX CPU, the MCP can process the instruction in par-
allel with and independent of the host CPU. When
the MCP detects an exception, it asserts the ER-
ROR
Y
signal, which causes a Intel386 DX CPU in-
terrupt.
3.3.5 SYNCHRONOUS OR ASYNCHRONOUS
MODES
The internal logic of the Intel387 DX MCP (the FPU)
can either operate directly from the CPU clock (syn-
chronous mode) or from a separate clock (asynchro-
nous mode). The two configurations are distin-
guished by the CKM pin. In either case, the bus con-
trol logic (BCL) of the MCP is synchronized with the
CPU clock. Use of asynchronous mode allows the
Intel386 DX CPU and the FPU section of the MCP to
run at different speeds. In this case, the ratio of the
frequency
of
NUMCLK2
CPUCLK2 must lie within the range 10:16 to 14:10.
Use of synchronous mode eliminates one clock gen-
erator from the board design.
to
the
frequency
of
3.3.6 AUTOMATIC BUS CYCLE TERMINATION
In configurations where no extra wait states are re-
quired, READYO
Y
can be used to drive the Intel386
DX CPU READY
Y
input. If this pin is used, it should
be connected to the logic that ORs all READY out-
puts from peripherals on the Intel386 DX CPU bus.
READYO
Y
is asserted by the MCP only during I/O
cycles that select the MCP. Refer to section 3.4
‘‘Bus Operation’’ for details.
3.4 Bus Operation
With respect to the bus interface, the Intel387 DX
MCP is fully synchronous with the Intel386 DX Mi-
croprocessor. Both operate at the same rate, be-
cause each generates its internal CLK signal by di-
viding CPUCLK2 by two.
The Intel386 DX CPU initiates a new bus cycle by
activating ADS
Y
. The MCP recognizes a bus cycle,
if, during the cycle in which ADS
Y
is activated,
STEN, NPS1
Y
, and NPS2 are all activated. Proper
operation is achieved if NPS1
Y
is connected to the
M/IO
Y
output of the Intel386 DX CPU, and NPS2 to
the A31 output. The Intel386 DX CPU’s A31 output
is guaranteed to be inactive in all bus cycles that do
not address the MCP (i.e. I/O cycles to other devic-
es, interrupt acknowledge, and reserved types of
bus cycles). System logic must not signal a 16-bit
bus cycle via the Intel386 DX CPU BS16
Y
input dur-
ing I/O cycles when A31 is active.
During the CLK period in which ADS
Y
is activated,
the MCP also examines the W/R
Y
input signal to
determine whether the cycle is a read or a write cy-
cle and examines the CMD0
Y
input to determine
whether an opcode, operand, or control/status reg-
ister transfer is to occur.
The Intel387 DX MCP supports both pipelined and
nonpipelined bus cycles. A nonpipelined cycle is one
for which the Intel386 DX CPU asserts ADS
Y
when
no other MCP bus cycle is in progress. A pipelined
bus cycle is one for which the Intel386 DX CPU as-
serts ADS
Y
and provides valid next-address and
control signals as soon as in the second CLK period
after the ADS
Y
assertion for the previous Intel386
DX CPU bus cycle. Pipelining increases the availabil-
ity of the bus by at least one CLK period. The MCP
supports pipelined bus cycles in order to optimize
address pipelining by the Intel386 DX CPU for mem-
ory cycles.
Bus operation is described in terms of an abstract
state machine. Figure 3.4 illustrates the states and
state transitions for MCP bus cycles:
#
T
I
is the idle state. This is the state of the bus
logic after RESET, the state to which bus logic
returns after evey nonpipelined bus cycle, and
the state to which bus logic returns after a series
of pipelined cycles.
#
T
RS
is the READY
Y
sensitive state. Different
types of bus cycle may require a minimum of one
or two successive T
RS
states. The bus logic re-
mains in T
RS
state until READY
Y
is sensed, at
which point the bus cycle terminates. Any number
of wait states may be implemented by delaying
READY
Y
, thereby causing additional successive
T
RS
states.
#
T
P
is the first state for every pipelined bus cycle.
240448–9
Figure 3.4. Bus State Diagram
25
25
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| INTEL82801 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82801AB (ICH0) I/O Controller Hub |
| INTEL82802AB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Firmware Hub (FWH) |
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