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參數(shù)資料
| 型號： | Intel387 dx |
| 廠商： | Intel Corp. |
| 英文描述： | DX Math Coprocessor(32位數(shù)學協(xié)處理器) |
| 中文描述： | 霉素數(shù)學協(xié)處理器（32位數(shù)學協(xié)處理器） |
| 文件頁數(shù)： | 12/41頁 |
| 文件大?。?/td> | 406K |
| 代理商： | INTEL387 DX |
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Intel387
TM
DX MATH COPROCESSOR
2.3.4 INSTRUCTION AND DATA POINTERS
Because the MCP operates in parallel with the CPU,
any errors detected by the MCP may be reported
after the CPU has executed the ESC instruction
which caused it. To allow identification of the failing
numeric instruction, the Intel386 DX Microprocessor
and Intel387 DX Math CoProcessor contains two
pointer registers that supply the address of the fail-
ing numeric instruction and the address of its numer-
ic memory operand (if appropriate).
The instruction and data pointers are provided for
user-written error handlers. These registers are ac-
tually located in the Intel386 DX CPU, but appear to
be located in the MCP because they are accessed
by the ESC instructions FLDENV, FSTENV, FSAVE,
and FRSTOR. (In the 8086/8087 and 80286/80287,
these registers are located in the MCP.) Whenever
the Intel386 DX CPU decodes a new ESC instruc-
tion, it saves the address of the instruction (including
any prefixes that may be present), the address of
the operand (if present), and the opcode.
The instruction and data pointers appear in one of
four formats depending on the operating mode of
the Intel386 DX Microprocessor (protected mode or
real-address mode) and depending on the operand-
size attribute in effect (32-bit operand or 16-bit oper-
and). When the Intel386 DX Microprocessor is in vir-
tual-8086 mode, the real-address mode formats are
used. (See Figures 2.3 through 2.6.) The ESC in-
structions FLDENV, FSTENV, FSAVE, and FRSTOR
are used to transfer these values between the In-
tel386 DX Microprocessor registers and memory.
Note that the value of the data pointer isundefined if
the prior ESC instruction did not have a memory op-
erand.
32-BIT PROTECTED MODE FORMAT
15
31
23
7
0
RESERVED
CONTROL WORD
0
RESERVED
STATUS WORD
4
RESERVED
TAG WORD
8
IP OFFSET
C
00000
OPCODE
10..0
CS SELECTOR
10
DATA OPERAND OFFSET
14
RESERVED
OPERAND SELECTOR
18
Figure 2.3. Protected Mode Intel387
TM
DX MCP Instruction and
Data Pointer Image in Memory, 32-Bit Format
12
12
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel387 sx | SX Math Coprocessor(32位數(shù)學協(xié)處理器) |
| INTEL486 GX | Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) |
| INTEL486 SX | Emedded Ultra-Low Power INTEL486 SX Processor(嵌入式超低能量處理器) |
| INTEL82801 | 82801AB (ICH0) I/O Controller Hub |
| INTEL82802AB | Firmware Hub (FWH) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
| INTEL740 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Graphics (GUI) Accelerator |
| INTEL82801 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82801AB (ICH0) I/O Controller Hub |
| INTEL82802AB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Firmware Hub (FWH) |
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