參數(shù)資料
型號(hào)： IMC020FLSP
廠商： INTEL CORP
元件分類(lèi)： DRAM
英文描述： 20 MegaBaytes Series 2+ Flash Memory Card(20M字節(jié)閃速存儲(chǔ)器卡)
中文描述： 10M X 16 FLASH 12V PROM CARD, 250 ns, XMA68
文件頁(yè)數(shù)： 5/41頁(yè)
文件大?。?/td> 575K
代理商： IMC020FLSP
E
1.0
SERIES 2+ FLASH MEMORY CARDS
5
SCOPE OF DOCUMENT
The documentation for Intel’s Series 2+ Flash
Memory Card includes this datasheet and the
Series 2+ Flash Memory Card User’s Manual
(297373). The datasheet provides all AC and DC
characteristics (including timing waveforms) and a
convenient reference for the device command set
and the card’s integrated registers (including the
28F016SA’s status registers). The
Series 2+
Memory Card User’s Manual
provides a complete
description of the methods for using the card. It
also contains the full list of software algorithms
and flowcharts and a section for upgrading Intel’s
Series 2 Flash Memory Cards designs.
2.0
PRODUCT OVERVIEW
The 4-, 8-, and 20-Mbyte Series 2+ Flash Memory
Cards each contain a flash memory array that
consists of two, four, and ten 28F016SA TSOP
memory devices, respectively. Each 28F016SA
contains 32 distinct, individually-erasable, 64-
Kbyte blocks. Therefore, the 4-, 8-, and 20-Mbyte
cards contain 64, 128 and 320 independantly
lockable blocks, respectively.
The 40-Mbyte Series 2+ Flash Memory Cards
contain a flash memory array that consists of ten
DD28F032SA TSOP memory devices. Each
DD28F032SA contains two 28F016SA die in a
single
package,
resulting
individually-erasable, 64-Kbyte blocks. The 40-
Mbyte cards have 640 independently lockable
blocks.
in
64
distinct,
The Series 2+ Card offers additional product
features to those of the Series 2 Card family (refer
to the iMC0XXFLSA datasheets). Some of the
more notable card-level enhancements include:
interchangeable operation at 3.3 V or 5.0 V, block
locking and internal V
PP
generation.
The Series 2+ card incorporates V
detect
circuitry, referred to as SmartPower, to sense the
voltage level present at the card interface. The
card’s control logic automatically configures its
circuitry and the 28F016SA/DD28F032SA memory
array accordingly. The Card Information Structure
(CIS) reports that the card is 3.3 V or 5.0 V
compatible. The card also detects the presence of
12.0 V on the V
pin and passes this supply to
each memory device. When the 12.0 V power
supply is unavailable, the card can generate the
required V
via its internal V
generation
circuitry, whether V
CC
is 3.3 V or 5.0 V.
At the device level, internal algorithm automation
allows write and erase operations to be executed
using a two-write command sequence in the same
way as the 28F008SA FlashFile memory in the
Series 2 Card. A super-set of commands and
additional performance enhancements have been
added to the basic 28F008SA command set:
Page Buffer Write to Flash results in writes up
to four times faster than Series 2 Cards.
Command Queueing permits the devices to
receive new commands during the execution
of the current command set.
Automatic data writes during erase allows the
28F016SA to perform write operations to one
block of memory while performing an erase on
another block.
Software locking of memory blocks provides a
means to selectively protect code or data
within the card.
Erase all unlocked blocks provides a quick
and simple method to sequentially erase all
the blocks within a 28F016SA memory device.
The Series 2+ Card has two ways to put the flash
devices into a sleep mode for reduced power
consumption:
1.
Issue a command to individual devices,
referred to as the software-controlled sleep
mode. The device will retain status register
data contents and finish any operation in
progress using this approach.
Write to the card’s PCMCIA-compatible
configuration and status register to activate a
reset
power-down
simultaneously.
2.
to
all
devices
The card achieves its PCMCIA-compatible word-
wide
access
by
pairing
DD28F032SA devices resulting in an accessible
memory block size of 64 Kwords. The card’s
decoding logic (contained within the ASICs) allows
the system to write or read one word at a time, or
one byte at a time by referencing the high or low
byte. Erasure can be performed on the entire
block pair (high and low byte simultaneously) or on
the high and low portions separately. Although the
28F016SA/DD28F032SA support byte or word-
wide data access, the byte interface was utilized
within the card to allow the delivery of higher
the
28F016SA/
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