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參數(shù)資料
| 型號： | IMC020FLSP |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 20 MegaBaytes Series 2+ Flash Memory Card(20M字節(jié)閃速存儲器卡) |
| 中文描述： | 10M X 16 FLASH 12V PROM CARD, 250 ns, XMA68 |
| 文件頁數(shù)： | 23/41頁 |
| 文件大?。?/td> | 575K |
| 代理商： | IMC020FLSP |
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E
7.0
SERIES 2+ FLASH MEMORY CARDS
23
SYSTEM DESIGN
CONSIDERATIONS
7.1
Power Supply Decoupling
Flash memory power-switching characteristics
require
careful
device
designers are interested in three supply current
issues: standby, active and transient current peaks
which are produced by rising and falling edges of
CE
# and CE
#. The capacitive and inductive loads
on the card and internal flash memory device pairs
determine the magnitudes of these peaks.
decoupling.
System
Three-line control and proper decoupling capacitor
selection
suppress
transient
Series
2+
cards
contain
decoupling capacitors connected between V
CC
and
GND, and between V
PP1
/V
PP2
and GND.
voltage
on-card
peaks.
ceramic
The card connector should also have a 4.7 μF
electrolytic capacitor between V
and GND, as
well as between V
/V
and GND. The bulk
capacitors overcome voltage slumps caused by
printed-circuit-board trace inductance, and supply
charge to the smaller capacitors as needed.
7.2
Power-Up/Down Protection
The PCMCIA/JEIDA-specified socket properly
sequences the power supplies to the flash memory
card via shorter and longer pins. This design
assures that hot insertion and removal will not
result in card damage or data loss.
Each device in the memory card is designed to
offer protection against accidental erasure or
writing, caused by spurious system-level signals
that may exist during power transitions. The card
will power-up into the read state.
A system designer must guard against active writes
for V
voltages above V
LKO
when V
is active.
Since both WE# and CE
# must be low for a
command write, driving either to V
will inhibit
writes. With its control register architecture,
alteration of device contents only occurs after
successful completion of the two-step command
sequences. While these precautions are sufficient
for most applications, an alternative approach
would allow V
to reach its steady state value
before raising V
/V
above V
CC
+ 2.0 V. In
addition, upon powering down, V
PP2
should be
below V
CC
+ 2.0 V before lowering V
CC
NOTE
The Integrated V
generator defaults to the
power off condition after reset and system
power-up. The V
PP
Generation circuitry must
be enabled for the memory card to operate in
3.3 V-only or 5.0 V-only mode.
7.3
Hot Insertion/Removal
The capability to remove or insert PC cards while
the
system
is
powered
insertion/removal)
requires
approaches on the system and card levels. To
design for this capability, consider card over-
voltage stress, system power fluxuations and
control line stability.
on
careful
(i.e.,
hot
design
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