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E
iMC002/004/010/020FLSA
3
PRELIMINARY
CONTENTS
PAGE
PAGE
1.0 APPLICATIONS..............................................5
2.0 SERIES 2 ARCHITECTURE OVERVIEW.......7
3.0 PCMCIA/JEIDA INTERFACE .........................7
4.0 WRITE PROTECT SWITCH.......................... 11
5.0 BATTERY VOLTAGE DETECT.................... 11
6.0 CARD DETECT............................................. 11
7.0 DESIGN CONSIDERATIONS ....................... 11
8.0 ADDRESS DECODE..................................... 12
9.0 DATA CONTROL.......................................... 12
10.0 PRINCIPLES OF OPERATON.................... 12
11.0 COMMON MEMORY ARRAY..................... 14
12.0 HARDWIRED CIS....................................... 14
13.0 COMPONENT MANAGEMENT REGISTERS
(CMRs)......................................................... 14
13.1 Soft Reset Register (PCMCIA) ................ 14
13.2 Global Power-Down Register (PCMCIA).. 15
13.3 Card Status Register (Intel) ..................... 16
13.4 Write Protection Register (Intel)............... 17
13.5 Sleep Control Register (Intel)................... 18
13.6 Ready-Busy Status Register (Intel).......... 18
13.7 Ready-Busy Mask Register (Intel) ........... 19
13.8 Ready-Busy Mode Register (Intel)........... 20
14.0 PRINCIPLES OF DEVICE OPERATION..... 21
15.0 COMMAND DEFINITIONS.......................... 23
15.1 Read Array (FFH).................................... 23
15.2 Intelligent Identifier (90H)......................... 23
15.3 Read Status Register (70H)..................... 23
15.4 Clear Status Register (50H)..................... 23
15.5 Write Setup/Write..................................... 23
15.6 Erase Setup/Erase Confirm Commands
(20H) ........................................................ 24
15.7 Erase Suspend (B0H)/Erase Resume
(D0H)........................................................ 24
15.8 Invalid/Reserved......................................24
16.0 DEVICE STATUS REGISTER.....................25
17.0 POWER CONSUMPTION ...........................28
17.1 Standby Mode..........................................28
17.2 Sleep Mode..............................................29
18.0 SYSTEM DESIGN CONSIDERATIONS......29
18.1 Power Supply Decoupling........................29
19.0 POWER UP/DOWN PROTECTION.............29
20.0 HOT INSERTION/REMOVAL......................29
21.0 PCMCIA CARD INFORMATION
STRUCTURE ...............................................29
21.1 The Device Information Tuple..................29
21.2 The Device Geometry Tuple ....................30
21.3 Jedec Programming Information Tuple ....30
21.4 Level 1 Version/Product Information
Tuple.........................................................30
21.5 The Configurable Card Tuple...................31
21.6 The End-of-List Tuple ..............................31
22.0 ELECTRICAL SPECIFICATIONS...............35
22.1 Absolute Maximum Ratings .....................35
22.2 Operating Conditions ...............................35
22.3 Capacitance.............................................35
22.4 Common DC Characteristics
—CMOS and
TTL...........................................................36
22.5 DC Characteristics—CMOS.....................37
22.6 DC Characteristics—TTL.........................39
22.7 AC Characteristics...................................40
23.0 ORDERING INFORMATION .......................51
24.0 ADDITIONAL INFORMATION.....................51