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參數(shù)資料
| 型號(hào)： | IMC004FLSA |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 Volt Series 2 Flash Memory Card(5V系列2閃速存儲(chǔ)器卡) |
| 中文描述： | 2M X 16 FLASH 12V PROM CARD, 150 ns, XMA68 |
| 文件頁數(shù)： | 20/51頁 |
| 文件大?。?/td> | 827K |
| 代理商： | IMC004FLSA |
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iMC002/004/010/020FLSA
E
20
PRELIMINARY
If the ready-busy mask register bits are set to ones
(masked condition), the RDY/BSY# output and the
card status register RDY/BSY# bit will reflect a
READY condition regardless of the state of the
corresponding devices. The ready-busy mask
register does not affect the ready-busy status
register allowing software polling to determine
operation status.
Unmasked is the default condition for the bits in this
register. On memory cards with fewer than 20
devices, unused device mask bits appear as
masked.
13.8
Ready-Busy Mode Register
(Intel)
The ready-busy mode register (Attribute Memory
Plane Address 4140H, Figure 12) provides the
selection of two types of system interfacing for the
busy-to-ready transition of the card’s RDY/BSY#
pin:
1.
The standard PCMCIA ready-busy mode, in
which the card’s RDY/BSY# signal generates a
low-to-high transition (from busy to ready) only
after
all
busy devices (not including masked
devices) have completed their data-write or
block-erase operations. This may result in a
long interrupt latency.
A high-performance mode that generates a low-
to-high (from busy-to-ready) transition after
each device becomes ready. This provides the
2.
host system with immediate notification that a
specific device’s operation has completed and
that device may now be used. This is
particularly useful in a file management
application where a block pair, containing only
deleted files, is being erased to free up space
so new file data may be written.
Enabling the high-performance ready-busy mode
requires a three step sequence:
1.
Set all bits in the ready/busy mask register.
This prevents ready devices from triggering an
unwanted interrupt when step 3 is performed.
Write 01H to the ready-busy mode register.
This sets the mode bit.
Write 01H to the ready-busy mode register.
This clears the RACK bit.
2.
3.
The mode and rack bits
must
be written in the
prescribed sequence,
not
simultaneously. The
card’s circuitry is designed purposely in this manner
to prevent an initial, unwanted busy-to-ready
transition. Note that in Step 2, writing to the rack bit
is a “Don’t Care.”
When the high-performance mode is enabled,
specific READY-BUSY MASK bits must be cleared
after an operation is initiated on the respective
devices. After each device becomes ready, the
RDY/BSY# pin makes a low-to-high transition. To
catch the next device’s completion of an operation,
the rack bit must be cleared by writing “01H” to the
ready-busy mode register.
READY-BUSY MODE REGISTER
(Read/Write Register)
MODE = READ-BUSY MODE
0 = PCMCIA MODE
1 = HIGH PERFORMANCE
RACK = READY ACKNOWLEDGE CLEAR TO SET UP RDY/BSY# PIN, THEN CLEAR
AFTER EACH DEVICE BECOMES READY TO ACKNOWLEDGE TRANSITION.
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 4
BIT 2
BIT 1
BIT 0
RACK
4140H
RESERVED FOR FUTURE USE
MODE
FIG12
Figure 12. High Performance Ready-Busy Mode Register (Intel)
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