825
32099I–01/2012
AT32UC3L016/32/64
Fix/Workaround
If the target frequency is below 30MHz, use a max step size (DFLL0MAXSTEP.MAXSTEP)
of seven or lower.
7.
Generic clock sources are kept running in sleep modes
If a clock is used as a source for a generic clock when going to a sleep mode where clock
sources are stopped, the source of the generic clock will be kept running. Please refer to
Power Manager chapter for details about sleep modes.
Fix/Workaround
Disable generic clocks before going to sleep modes where clock sources are stopped to
save power.
8.
DFLL clock is unstable with a fast reference clock
The DFLL clock can be unstable when a fast clock is used as a reference clock in closed
loop mode.
Fix/Workaround
Use the 32KHz crystal oscillator clock, or a clock with a similar frequency, as DFLLIF refer-
ence clock.
9.
DFLLIF indicates coarse lock too early
The DFLLIF might indicate coarse lock too early, the DFLL will lose coarse lock and regain it
later.
Fix/Workaround
Use max step size (DFLL0MAXSTEP.MAXSTEP) of 4 or higher.
10. DFLLIF dithering does not work
The DFLLIF dithering does not work.
Fix/Workaround
None.
11. DFLLIF might lose fine lock when dithering is disabled
When dithering is disabled and fine lock has been acquired, the DFLL might lose the fine
lock resulting in up to 20% over-/undershoot.
Fix/Workaround
Solution 1: When the DFLL is used as main clock source, the target frequency of the DFLL
should be 20% below the maximum operating frequency of the CPU. Don’t use the DFLL as
clock source for frequency sensitive applications.
Solution 2: Do not use the DFLL in closed loop mode.
12. GCLK5 is non-functional
GCLK5 is non-functional.
Fix/Workaround
None.
13. BRIFA is non-functional
BRIFA is non-functional.
Fix/Workaround
None.
14. SCIF VERSION register reads 0x100
SCIFVERSION register reads 0x100 instead of 0x102.
Fix/Workaround
None.