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型號(hào)：	IF280C52EXXX-16SHXXX:RD
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44
文件頁(yè)數(shù)：	103/849頁(yè)
文件大?。?/td>	12530K

32099I–01/2012

AT32UC3L016/32/64

the Fractional Multiply field (FMUL) in the DFLLn Multiplier Register (DFLLnMUL). Care must be

taken when choosing IMUL and FMUL so the output frequency does not exceed the maximum

frequency of the device. Start the closed loop mode by writing a one to DFLLnCONF.MODE bit.

The frequency of CLK_DFLL (f

DFLL) is given by:

REF is the frequency of CLK_DFLLIF_REF. COARSE and FINE in DFLLnCONF are read-

only in closed loop mode, and are controlled by the DFLLIF to meet user specified frequency.

The values in COARSE when the closed loop mode is enabled is used by the frequency tuner as

a starting point for COARSE. Setting COARSE to a value close to the final value will reduce the

time needed to get a lock on COARSE.

Frequency locking

The locking of the frequency in closed loop mode is divided into three stages. In the COARSE

stage the control logic quickly finds the correct value for DFLLnCONF.COARSE and thereby

sets the output frequency to a value close to the correct frequency. The DFLLn Locked on

Coarse Value bit (DFLLnLOCKC) in PCLKSR will be set when this is done. In the FINE stage the

control logic tunes the value in DFLLnCONF.FINE so the output frequency will be very close to

the desired frequency. DFLLn Locked on Fine Value bit (DFLLnLOCKF) in PCLKSR will be set

when this is done. In the ACCURATE stage the DFLL frequency tuning mechanism uses dither-

ing on the FINE bits to obtain an accurate average output frequency. DFLLn Locked on Accurate

Value bit (DFLLnLOCKA) in PCLKSR will be set when this is done. The ACCURATE stage will

only be executed if the Dithering Enable bit (DITHER) in DFLLnCONF has been written to a one.

If DITHER is written to a zero DFLLnLOCKA will never occur. If dithering is enabled, the fre-

quency of the dithering is decided by a generic clock (CLK_DFLLIF_DITHER). This clock has to

be set up correctly before enabling dithering. Please refer to the Generic Clocks section for

Figure 13-2. DFLL Closed loop State Diagram

When dithering is enabled the accuracy of the average output frequency of the DFLL will be

higher. However, the actual frequency will be alternating between two frequencies. If a fixed fre-

quency is required, the dithering should not be enabled.

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
IF280C52-L16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
IF280C52T-12	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
IF280C52T-16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
IF280C52T-20	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
IF280C52T-25	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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