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型號(hào)：	IF280C52EXXX-16SHXXX:RD
廠商：	TEMIC SEMICONDUCTORS
元件分類(lèi)：	微控制器/微處理器
英文描述：	8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44
文件頁(yè)數(shù)：	806/849頁(yè)
文件大?。?/td>	12530K

32099I–01/2012

AT32UC3L016/32/64

- The OSC0 is enabled in external clock mode (OSCCTRL0.OSCEN == 1 and

OSCCTRL0.MODE == 0)

- A sleep mode where the OSC0 is automatically disabled is entered

- The device enters sleep walking

Fix/Workaround

Do not run OSC0 in external clock mode if sleepwalking is expected to be used.

10. Sleepwalking in idle and frozen sleep mode will mask all other PB clocks

If the CPU is in idle or frozen sleep mode and a module is in a state that triggers sleep walk-

ing, all PB clocks will be masked except the PB clock to the sleepwalking module.

Fix/Workaround

Mask all clock requests in the PM.PPCR register before going into idle or frozen mode.

11. VERSION register reads 0x400

The VERSION register reads 0x400 instead of 0x411.

Fix/Workaround

The DFLL should be slowed down before disabling it

The frequency of the DFLL should be set to minimum before disabling it.

Fix/Workaround

Before disabling the DFLL the value of the COARSE register should be zero.

Writing to ICR masks new interrupts received in the same clock cycle

Writing to ICR masks any new SCIF interrupt received in the same clock cycle, regardless of

write value.

Fix/Workaround

For every interrupt except BODDET, SM33DET, and VREGOK the PCLKSR register can be

read to detect new interrupts. BODDET, SM33DET and VREGOK interrupts will not be gen-

erated if they occur whilst writing to the ICR register.

FINE value for DFLL is not correct when dithering is disabled

In open loop mode, the FINE value used by the DFLL DAC is offset by two compared to the

value written to the DFLL0CONF.FINE field. The value used by the DFLL DAC is

DFLL0CONF.FINE-0x002. If DFLL0CONF.FINE is written to 0x000, 0x001 or 0x002 the

value used by the DFLL DAC will be 0x1FE, 0x1FF, or 0x000 respectively.

Fix/Workaround

Write the desired value added by two to the DFLL0CONF.FINE field.

BODVERSION register reads 0x100

The BODVERSION register reads 0x100 instead of 0x101

Fix/Workaround

VREGCR.DEEPMODEDISABLE bit is not readable

VREGCR.DEEPMODEDISABLE bit is not readable.

Fix/Workaround

DFLL step size should be seven or lower when below 30MHz

If max step size is above seven, the DFLL might not lock at the correct frequency if the tar-

get frequency is below 30MHz.

相關(guān)PDF資料	PDF描述
MR80C52CXXX-36SHXXX:R	8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44
MQ80C52CXXX-12/883:R	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44
MQ80C52CXXX-25P883R	8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44
MQ80C52CXXX-25P883R	8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44
MQ80C154-16P883D	8-BIT, 16 MHz, MICROCONTROLLER, CQFP44

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
IF280C52-L16	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller
IF280C52T-12	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller
IF280C52T-16	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller
IF280C52T-20	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller
IF280C52T-25	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller

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