參數(shù)資料
型號(hào): IDTSSTE32882HLBBKG
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 59/73頁(yè)
文件大?。?/td> 0K
描述: IC REGISTERING CLK DRIVER 176BGA
標(biāo)準(zhǔn)包裝: 208
類型: 時(shí)鐘緩沖器/驅(qū)動(dòng)器,多路復(fù)用器
PLL:
主要目的: 存儲(chǔ)器,DDR3,RDIMM
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 5:60
差分 - 輸入:輸出: 是/是
頻率 - 最大: 810MHz
電源電壓: 1.282 V ~ 1.575 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 176-TFBGA
供應(yīng)商設(shè)備封裝: 176-CABGA(6x15)
包裝: 托盤
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
62
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
RC5: CK Driver Characteristics Control Word
RC8: Additional IBT Setting Control Word
Input
Definition
Encoding
DBA1
DBA0
DA4
DA3
xx
0
Clock Y1, Y1, Y3, and Y3
Output Drivers
Light Drive (4 or 5 DRAM Loads)
x
0
1
Moderate Drive (8 or 10 DRAM Loads)
x
1
0
Strong Drive (16 or 20 DRAM Loads)
xx
1
Reserved
00
x
Clock Y0, Y0, Y2, and Y2
Output Drivers
Light Drive (4 or 5 DRAM Loads)
0
1
x
Moderate Drive (8 or 10 DRAM Loads)
1
0
x
Strong Drive (16 or 20 DRAM Loads)
11
x
Reserved
Input
Definition
Encoding
DBA1
DBA0
DA4
DA3
x0
0
IBT Compatibility Settings
IBT as defined in RC2
0x
x
Mirror Mode
IBT Off when MIRROR is HIGH1
1
If MIRROR is HIGH, then Input Bus Termination (IBT) is turned off on all inputs, except DCSn and DOD-
Tn inputs.
1x
x
IBT On when MIRROR is HIGH2
2
When DBA0 = 1, DA4 = 1, or DA3 = 1, IBT on all inputs is turned off no matter what the DBA1 setting
may be.
x0
0
1
Input Bus Termination1
Reserved
x0
1
0
200
x0
1
Reserved
x1
0
300
x1
0
1
Reserved
x1
1
0
Reserved
x1
1
Off3
3
With this setting, no matter what the logic level of the MIRROR input pin may be, IBT on all inputs (in-
cluding DCSn and DODTn) is turned off.
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