參數(shù)資料
型號(hào): IDTSSTE32882HLBBKG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 12/73頁
文件大?。?/td> 0K
描述: IC REGISTERING CLK DRIVER 176BGA
標(biāo)準(zhǔn)包裝: 208
類型: 時(shí)鐘緩沖器/驅(qū)動(dòng)器,多路復(fù)用器
PLL:
主要目的: 存儲(chǔ)器,DDR3,RDIMM
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 5:60
差分 - 輸入:輸出: 是/是
頻率 - 最大: 810MHz
電源電壓: 1.282 V ~ 1.575 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 176-TFBGA
供應(yīng)商設(shè)備封裝: 176-CABGA(6x15)
包裝: 托盤
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
2
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Features
Pinout optimizes DDR3 RDIMM PCB layout
1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs
Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs
Supports LVCMOS switching levels on the RESET and MIRROR inputs
Checks priority on DIMM-independent data inputs
Supports dynamic 1T/3T timing transaction and output inversion feature for improved timing performance during normal operations
and MRS command pass-through
Supports CKE Power Down operation modes
Supports Quad Chip Select operation features
RESET input disables differential input recievers, resets all registers, and disables all output drivers except ERROUT and QnCKEn
Provides access to internal control words for configuring the device features and adapting in different RDIMM and system
applications
Latch-up performance exceeds 100mA
ESD > 2000V per MIL-STD883, Method 3015; ESD > 200V using machine model (c = 200pF, R = 0)
Available in 176 Ball Grid Array package
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDTSSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA
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