參數(shù)資料
型號: IDTSSTE32882HLBBKG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 50/73頁
文件大?。?/td> 0K
描述: IC REGISTERING CLK DRIVER 176BGA
標準包裝: 208
類型: 時鐘緩沖器/驅動器,多路復用器
PLL:
主要目的: 存儲器,DDR3,RDIMM
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 5:60
差分 - 輸入:輸出: 是/是
頻率 - 最大: 810MHz
電源電壓: 1.282 V ~ 1.575 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 176-TFBGA
供應商設備封裝: 176-CABGA(6x15)
包裝: 托盤
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
54
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Control Words
The device features a set of control words, which allow the optimization of the device properties for different raw card designs.
The different control words and settings are described below. Any change to these control words requires some time for the
device to settle. For changes to the control word setting, except for RC2 (bits DBA1 and DA3) and RC10, the controller needs
to wait tMRD after the last control word access, before further access to the DRAM can take place. For any changes to the clock
timing (RC2: bits DBA1 and DA3) and RC10, this settling may take up to tSTAB time. All chip select inputs (DCS[n:0]) must
be kept high during that time. The Control Words can be accessed and written to when running within any one defined
frequency band.
CONTROL WORD DECODING
The values to be programmed into each control word are presented on signals DA3, DA4, DBA0 and DBA1 simultaneously
with the assertion of the control word access through DCS0 and DCS1, or DCS2 and DCS3 in the QuadCS enabled mode, and
the address of the control word on DA0, DA1, DA2 and DBA2.
The reset default state of Control Words 0 .. 5 and Control Words 8 .. 15 is “0”. The reset default state for Control Words 6 and
7 is vendor specific. Every time the device is reset, its default state is restored. Stopping the clocks (CK = CK = low) to put the
device in low-power mode will not alter the control word settings.
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