參數(shù)資料
型號(hào): IDTSSTE32882HLBBKG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 11/73頁
文件大?。?/td> 0K
描述: IC REGISTERING CLK DRIVER 176BGA
標(biāo)準(zhǔn)包裝: 208
類型: 時(shí)鐘緩沖器/驅(qū)動(dòng)器,多路復(fù)用器
PLL:
主要目的: 存儲(chǔ)器,DDR3,RDIMM
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 5:60
差分 - 輸入:輸出: 是/是
頻率 - 最大: 810MHz
電源電壓: 1.282 V ~ 1.575 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 176-TFBGA
供應(yīng)商設(shè)備封裝: 176-CABGA(6x15)
包裝: 托盤
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
19
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Parity, Low Power and Standby with QuadCS Mode Enabled
Inputs
Output
RESET
DCS[3:0]
CK1
1
It is illegal to hold both the CK and CK inputs at static logic high levels or static complementary logic levels (low
and high) when RESET is driven high.
CK1
of A/C2
2
A/C = DA0..DA15, DBA0..DBA2, DRAS, DCAS, DWE. Inputs DCKE0, DCKE1, DODT0, DODT1, DCS0
and DCS1 are not included in this range. This column represents the sum of the number of A/C signals that are elec-
trically high.
PAR_IN3
3
PAR_IN arrivesone clock cycle afterdata to which it applies, ERROUT is issued three clock cycles after the fail-
ing data.
ERROUT4
4
This transition assumes ERROUT is high at the crossing of CK going high and CK going low. If ERROUT is
low, it stays latched low for exactly two clock cycles or until RESET is driven low.
HLXXX
XLXX
XXLX
XXXL
Even
L
H
HLXXX
XLXX
XXLX
XXXL
Odd
L
HLXXX
XLXX
XXLX
XXXL
Even
H
L
HLXXX
XLXX
XXLX
XXXL
Odd
H
HHHH
XX
H5
5
Same three-cycle delay for ERROUT is valid for the de-select phase (see diagram)
H
XXXX
L or H
H or L
X
ERROUTn0
H
XXXX
L
X
H6
6
The system is not allowed to pull CK and CK low while ERROUT is asserted.
L
X or floating
X or floating X or floating X or floating X or floating
H
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