- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9596 > IDTSSTE32882HLBAKG (IDT, Integrated Device Technology Inc)IC REGISTERING CLK DRIVER 176BGA PDF資料下載
參數(shù)資料
| 型號(hào)： | IDTSSTE32882HLBAKG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 37/73頁 |
| 文件大小： | 0K |
| 描述： | IC REGISTERING CLK DRIVER 176BGA |
| 標(biāo)準(zhǔn)包裝： | 170 |
| 類型： | 時(shí)鐘緩沖器/驅(qū)動(dòng)器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 存儲(chǔ)器，DDR3，RDIMM |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:60 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 810MHz |
| 電源電壓： | 1.282 V ~ 1.575 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 176-CABGA（13.5x8） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當(dāng)前第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
42
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Parity-Error Occurrences During Control Word Programming
1 CK left out for better visibility.
POWER SAVING MODES
The device supports different power saving mechanisms.
When both inputs CK and CK are being held low the device stops operation and enters low-power static and standby operation.
It stops its PLL and floats all outputs except QACKE0, QACKE1, QBCKE0 and QBCKE1 which are kept driven low. Before
the device is taken out of standby operation by applying a stable input clock signal, the register inputs DCS[n:0] must be pulled
high to prevent accidential access to the control registers and DCKE0 as well as DCKE1 must be pulled low for a certain period
of time (tACT). The input clock must be stable for a time (tSTAB) before any access to the device takes place. Stopping the
clocks (CK = CK = low) will only put the SSTE32882HLB in low-power mode and will not clear the content of the control
words. The control words will reset only when RESET is diven low.
A float feature can be enabled by setting the corresponding bit in the control register. This causes the device to monitor all the
DCS[n:0] inputs and to float all outputs corresponding with the chip select gated inputs when all the DCS[n:0] inputs are high.
If any one of the DCS[n:0] inputs are low, the Qn outputs will function normally.
Once all the DCS[n;0] inputs are high, the gated address command inputs to the register can float to conserve input termination
power. DCKE0, DCKE1, DODT0 and DODT1 need to be driven by the system all the time.
The RESET input has priority over all other power saving mechanisms. When RESET is driven low, it will force the Qn
outputs to float, the ERROUT output high, the QACKE0, QACKE1, QBCKE0 and QBCKE1 outputs low, and disables Input
Bus Termination (IBT).
REGISTER CKE POWER DOWN
If RC9[DBA1] is set to “1”, the SSTE32882HLB monitors both DCKEn input signals and enters into power saving state when
it latches Low on both DCKEn inputs and at least one of the DCKEn input has transitioned from High to Low. If any input
Chip Select signal (DCS[n:0]) is asserted together with DCKEn, the SSTE32882HLB transfers the corresponding command to
its outputs together with QxCKEn Low.
There are two modes of CKE Power Down selected by RC9. Bit DBA0 in RC9 indicates whether the register turns off IBT or
keeps IBT on.
CK(1)
CA
Input
PAR_IN
CA0
P0
CA1
P1
CA2
P2
ERROUT
n
n+1
n+2
n+3
n+4
n+5
n+6
ERROUTresulting from CA0 - P0, followed by 2nd error during control word access in CA3 - P3
n+7
n+8
n+9
CA3
P3
P4
CA4
CA5
P5
DCS0
DCS1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISL81487IB-T | IC TXRX RS485/422 5V HS 8-SOIC |
| ISL81487IB | IC TXRX RS485/422 5V HS 8-SOIC |
| CS3108A-24-58P | CONN PLUG 13POS RT ANG W/PINS |
| CY28410ZXC | IC CLOCK CK410GRANTSDALE 56TSSOP |
| D38999/24WJ4SA | CONN RCPT 56POS JAM NUT W/SCKT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTSSTE32882HLBAKG8 | 功能描述:IC REGISTERING CLK DRIVER 176BGA RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| IDTSSTE32882HLBBKG | 功能描述:IC REGISTERING CLK DRIVER 176BGA RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDTSSTE32882HLBBKG8 | 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA |
| IDTSSTE32882KA1AKG | 功能描述:IC REGISTERING CLK DRIVER 176BGA RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDTSSTE32882KA1AKG8 | 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。