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參數(shù)資料
| 型號： | IDTSSTE32882HLBAKG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 29/73頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REGISTERING CLK DRIVER 176BGA |
| 標準包裝： | 170 |
| 類型： | 時鐘緩沖器/驅(qū)動器，多路復用器 |
| PLL： | 是 |
| 主要目的： | 存儲器，DDR3，RDIMM |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:60 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 810MHz |
| 電源電壓： | 1.282 V ~ 1.575 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-TFBGA |
| 供應商設備封裝： | 176-CABGA（13.5x8） |
| 包裝： | 托盤 |
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
35
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Clock Driver Characteristics at Test Frequency (frequency band 2)
Symbol
Parameter
Conditions
Min.
Max.
Unit
tJIT(CC)
Cycle-to-cycle period jitter
0
160
ps
tSTAB
Stabilization time
15
us
tCKSK
Total Clock Output skew1
1
This skew represents the absolute output clock skew and contains the pad skew and package skew.
100
ps
Fractional Clock Output skew2
2
This skew represents the absolute output clock skew and contains the pad skew and package skew (see “Clock Output (Yn)
Skew”). This parameter is specified for the clock pairs on each side of the register independently. The skew is applicable to the
left side of the clock pair between Y0/Y0 and Y2/Y2, as well as the right side of the clock pair between Y1/Y1 and Y3/Y3.
TBD
tJIT(PER)
Yn Clock Period jitter
-160
160
ps
tJIT(HPER)
Half period jitter
-200
200
ps
tQSK13
3
This skew represents the absolute Qn skew compared to the output clock Yn, and contains the register pad skew, clock skew,
and package routing skew (see “Qn Output Skew for Standard 1/2 Clock Pre-Launch”). The output clock jitter is not included in
this skew. This parameter applies to each side of the register independently. The Qn output can either be early or late.
Qn Output to clock tolerance (Standard
1/2-Clock Pre-Launch)
Output Inversion
Enabled
-100
TBD
ps
tQSK1SSO4
4
This skew represents the absolute Qn skew compared to the output clock Yn, and contains the register pad skew, clock skew,
and package routing skew. The output clock jitter is not included in this skew. This parameter applies to each side of the register
independently. This parameter includes the skew related to Simultaneous Switching Noise (SSO). The Qn output can either be
early or late.
Output Inversion
Disabled
-100
TBD
tQSK25
5
This skew represents the absolute Qn skew compared to the output clock Yn, and contains the register pad skew, clock skew,
and package routing skew (see “Qn Output Skew for Standard 3/4 Clock Pre-Launch”). The output clock jitter is not included in
this skew. This parameter applies to each side of the register independently. The Qn output can either be early or late.
Output clock tolerance (3/4 Clock Pre-Launch)
Output Inversion
Enabled
-100
TBD
ps
tQSK2SSO6
6
This skew represents the absolute Qn skew compared to the output clock Yn, and contains the register pad skew, clock skew,
and package routing skew. The output clock jitter is not included in this skew. This parameter applies to each side of the register
independently. This parameter includes the skew related to Simultaneous Switching Noise (SSO). The Qn output can either be
early or late.
Output Inversion
Disabled
-100
TBD
tDYNOFF
Maximum re-driven dynamic clock offset7
7 The re-driven clock signal is ideally centered in the address/control signal eye. This parameter describes the dynamic deviation
from this ideal position including jitter and dynamic phase offset.
-500
500
ps
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTSSTE32882HLBAKG8 | 功能描述:IC REGISTERING CLK DRIVER 176BGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| IDTSSTE32882HLBBKG | 功能描述:IC REGISTERING CLK DRIVER 176BGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDTSSTE32882HLBBKG8 | 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA |
| IDTSSTE32882KA1AKG | 功能描述:IC REGISTERING CLK DRIVER 176BGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDTSSTE32882KA1AKG8 | 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA |
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