參數(shù)資料
型號(hào): IDTSSTE32882HLBAKG8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 63/73頁(yè)
文件大?。?/td> 0K
描述: IC REGISTERING CLK DRIVER 176BGA
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘緩沖器/驅(qū)動(dòng)器,多路復(fù)用器
PLL:
主要目的: 存儲(chǔ)器,DDR3,RDIMM
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 5:60
差分 - 輸入:輸出: 是/是
頻率 - 最大: 810MHz
電源電壓: 1.282 V ~ 1.575 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 176-TFBGA
供應(yīng)商設(shè)備封裝: 176-CABGA(13.5x8)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 800-2597-6
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
66
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Voltage waveforms address floating
Refer to “Calculating the virtual VREF crossing point”.
Enabling and disabling the CA outputs must not violate DRAM setup and hold time requirements. Therefore a tDIS transition
may not occure earlier than a regular (HL/LH) transition and a tEN transition may not occure later than a regular (HL/LH)
transition. Regular transitions are measured between CK/CK and CA/VTT crossings however a VTT crossing is not available in
the state where the outputs are Hi-Z. To allow a correct and not overly conservative measurement a virtual VTT crossing point
is defined below. The calculation of the virtual VTT crossing point is shown in the Figure, “Calculating the virtual VTT crossing
point”. The voltage levels for yxa and yxb are measured from VTT (VDD/2) and should be selected such that the region between
t1 and t2 covers a linear range and represents a typical slope of the waveform within the transition area. They have to be used
signed in the formula.
Outputs
Yn
tDIS
tEN
VOX
VOD
CK
DCSn
QxCSn
virtual VTT crossing*
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IDTSSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA
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