參數(shù)資料
型號(hào)： IDTSSTE32882HLBAKG8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 39/73頁(yè)
文件大小： 0K
描述： IC REGISTERING CLK DRIVER 176BGA
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘緩沖器/驅(qū)動(dòng)器，多路復(fù)用器
PLL： 是
主要目的： 存儲(chǔ)器，DDR3，RDIMM
輸入： CMOS
輸出： CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 5:60
差分 - 輸入:輸出： 是/是
頻率 - 最大： 810MHz
電源電壓： 1.282 V ~ 1.575 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 176-TFBGA
供應(yīng)商設(shè)備封裝： 176-CABGA（13.5x8）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 800-2597-6
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
44
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
To re-enable the register from this power saving state, valid logic levels are required at all register inputs when either or both
DCKEn inputs are driven high. Upon either DCKE0 or DCKE1 input going High, the register immediately starts driving High
on the appropriate QxCKEn signal. The QxCSn signals are driven High and QxODTn signals are driven Low. Other output
signals QxRAS, QxCAS, QxWE, and QxAddr are driven either high or low to ensure stable valid logic an all register outputs
when QxCKEn goes High. The register drives output signals to these levels for tFIXEDOUTPUT to allow input receivers to be
stabilized. After the input recievers are stabilized, the register output follow their corresponding input levels. When exiting
CKE power down mode, either one of the Chip Select register inputs DCSn can be asserted for 1 tCK. For QuadCS capable
register, when working in quad rank mode, either two of the Chip Select register inputs DCSn can be asserted for 1 tCK. The
register guarantees that input receivers are stabilized within tFIXEDOUTPUT clocks after DCKEn input is driven High. This is
shown in the previous diagram.
REGISTER CKE POWER DOWN WITH IBT ON
Upon entry into CKE Power Down Mode with IBT on, all register input buffers excluding IBT are disabled except for CK/CK,
DCKEn, DODTn, FBIN/FBIN, and RESET. The SSTE32882HLB disables input buffers within tInDIS clocks after latching
both DCKEn Low. In order to eliminate any false parity check error, the PAR_IN input buffer has to be kept active for 1 tCK
after the Address and Command input buffers are disabled. After tInDIS, the register can tolerate floating input except for
CK/CK, DCKEn, DODTn and RESET. The SSTE32882HLB also disables all its output buffers except for Yn/Yn, QxODTn,
QxCKEn and FBOUT/FBOUT. The Yn/Yn and FBOUT/FBOUT outputs continue to drive a valid phase accurate clock signal.
The QxCKEn outputs are driven Low. The register output buffers are Hi-Z tQDIS clock after QxCKEn is driven Low. This is
shown below.
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參數(shù)描述
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IDTSSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA
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IDTSSTE32882KA1AKG8 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA
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