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參數(shù)資料
| 型號： | IDT8535-01PGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER |
| 中文描述： | 8535 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 4 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | TSSOP-16 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 85K |
| 代理商： | IDT8535-01PGI |
8
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT8535-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
APPLICATION INFORMATION
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termnation for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.
F
OUT
and xF
OUT
are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, termnating resistors (DC current path to
ground) or current sources must be used for functionality. These outputs are designed to drive 50
transmssion lines. Matched impedance techniques should
be used to maximze operating frequency and mnimze signal distortion. The diagrams below show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist. It is recommended that the board designers simulate to guarantee compatibility across all printed circuit and
clock component process variations.
LVPECL Output Termination, layout A
LVPECL Output Termination, layout B
F
OUT
50
50
Zo = 50
V
DD
- 2V
Zo = 50
R
TT
F
IN
R
TT
=
(V
OH
+ V
OL
/ V
DD
- 2) - 2
1
Zo
F
OUT
Zo = 50
Zo = 50
F
IN
Zo
3
2
Zo
3
2
Zo
5
2
Zo
5
2
3.3V
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