參數(shù)資料
型號(hào)： IDT8535-01PGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
中文描述： 8535 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 4 INVERTED OUTPUT(S), PDSO20
封裝： TSSOP-16
文件頁(yè)數(shù)： 2/11頁(yè)
文件大?。?/td> 85K
代理商： IDT8535-01PGI
2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT8535-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
PIN CONFIGURATION
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
ABSOLUTE MAX IMUM RATINGS
(1)
Symbol
Description
V
DD
Power Supply Voltage
V
I
Input Voltage
V
O
Output Voltage
θ
JA
Package Thermal Impedance (0 lfpm
T
STG
Storage Temperature
Max
4.6
Unit
V
V
V
°C/W
–0.5 to V
DD
+0.5
–0.5 to V
DD
+0.5
92.6
–65 to +150
°C
CAPACITANCE
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Parameter
Description
C
IN
Input Capacitance
R
PULLUP
Input Pullup Resistor
R
PULLDOWN
Input Pulldown Resistor
Typ.
—
51
51
Max.
4
—
—
Unit
pF
K
K
TSSOP
TOP VIEW
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
EE
CLK_EN
CLK_SEL
CLK0
NC
CLK1
NC
NC
NC
V
DD
Q0
xQ0
V
DD
Q1
xQ1
Q2
xQ2
V
DD
Q3
xQ3
PIN DESCRIPTION
(1)
Symbol
V
EE
CLK_EN
Number
1
2
Type
Description
PWR
Input
Negative Supply Pin
Synchronizing Clock Enable. When HIGH, clock outputs follow clock input. When
LOW, Q outputs are forced LOW, xQ outputs are forced HIGH. LVCMOS / LVTTL
interface levels.
Clock Select Input. When HIGH, selects CLK1 input. When LOW, selects CLK0
input. LVCMOS / LVTTL interface levels.
LVCMOS / LVTTL Clock Input
LVCMOS / LVTTL Clock Input
No Connection
Positive Supply Pins
Differential Output Pair. LVPECL interface levels.
Differential Output Pair. LVPECL interface levels.
Differential Output Pair. LVPECL interface levels.
Differential Output Pair. LVPECL interface levels.
Pullup
CLK_SEL
3
Input
Pulldown
CLK0
CLK1
NC
V
DD
xQ3, Q3
xQ2 Q2
xQ1, Q1
xQ0, Q0
4
6
Input
Input
Unused
Power
Output
Output
Output
Output
Pulldown
Pulldown
5, 7, 8, 9
10, 13, 18
11, 12
14, 15
16, 17
19, 20
NOTE:
1. Pullup and Pulldown refer to internal input resistors. See Capacitance table for typical values.
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