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參數(shù)資料
| 型號(hào)： | IDT8535-01PGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER |
| 中文描述： | 8535 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 4 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | TSSOP-16 |
| 文件頁(yè)數(shù)： | 3/11頁(yè) |
| 文件大?。?/td> | 85K |
| 代理商： | IDT8535-01PGI |
3
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT8535-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
CONTROL INPUT FUNCTION TABLE
(1,2)
Inputs
CLK_SEL
0
1
0
1
Outputs
CLK_EN
0
0
1
1
Selected Source
CLK0
CLK1
CLK0
CLK1
Q0 to Q3
Disabled; LOW
Disabled; LOW
Enabled
Enabled
xQ0 to xQ3
Disabled; HIGH
Disabled; HIGH
Enabled
Enabled
NOTES:
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in the CLK_EN Timng Diagrambelow.
2. In active mode, the state of the outputs is a function of the CLK / xCLK and PCLK / xPCLK inputs as described in the Clock Input Function table.
CLOCK INPUT FUNCTION TABLE
(1)
Inputs
CLK0 or CLK1
0
1
Outputs
Q0 to Q3
L
H
xQ0 to xQ3
H
L
NOTE:
1. H = HIGH
L = LOW
CLK EN
CLK0, CLK1
xQ0, xQ1, xQ2, xQ3
≈
≈
Disabled
Enabled
≈
Q0, Q1, Q2, Q3
CLK_EN Timing Diagram
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