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參數(shù)資料
| 型號(hào)： | IDT82V3288BCG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | WAN PLL |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA208 |
| 封裝： | GREEN, PLASTIC, CABGA-208 |
| 文件頁數(shù)： | 3/170頁 |
| 文件大?。?/td> | 1053K |
| 代理商： | IDT82V3288BCG |
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Table of Contents
3
June 22, 2006
FEATURES.............................................................................................................................................................................. 9
HIGHLIGHTS....................................................................................................................................................................................................9
MAIN FEATURES............................................................................................................................................................................................9
OTHER FEATURES.........................................................................................................................................................................................9
APPLICATIONS....................................................................................................................................................................... 9
DESCRIPTION....................................................................................................................................................................... 10
FUNCTIONAL BLOCK DIAGRAM........................................................................................................................................ 11
1 PIN ASSIGNMENT ...........................................................................................................................................................12
2 PIN DESCRIPTION ..........................................................................................................................................................13
3 FUNCTIONAL DESCRIPTION .........................................................................................................................................20
3.1
RESET ...........................................................................................................................................................................................................20
3.2
MASTER CLOCK & MASTER CLOCK MONITORING ................................................................................................................................20
3.3
INPUT CLOCKS & FRAME SYNC SIGNALS ...............................................................................................................................................21
3.3.1
Input Clocks .................................................................................................................................................................................... 21
3.3.2
Frame SYNC Input Signals ............................................................................................................................................................ 21
3.4
INPUT CLOCK PRE-DIVIDER ......................................................................................................................................................................22
3.5
INPUT CLOCK QUALITY MONITORING .....................................................................................................................................................24
3.5.1
LOS Monitoring .............................................................................................................................................................................. 24
3.5.2
Activity Monitoring ......................................................................................................................................................................... 24
3.5.3
Frequency Monitoring ................................................................................................................................................................... 25
3.6
T0 / T4 DPLL INPUT CLOCK SELECTION ..................................................................................................................................................26
3.6.1
External Fast Selection (T0 only) .................................................................................................................................................. 26
3.6.2
Forced Selection ............................................................................................................................................................................ 27
3.6.3
Automatic Selection ....................................................................................................................................................................... 27
3.7
SELECTED INPUT CLOCK MONITORING ..................................................................................................................................................28
3.7.1
T0 / T4 DPLL Locking Detection ................................................................................................................................................... 28
3.7.1.1
Fast Loss .......................................................................................................................................................................... 28
3.7.1.2
Coarse Phase Loss .......................................................................................................................................................... 28
3.7.1.3
Fine Phase Loss ............................................................................................................................................................... 28
3.7.1.4
Hard Limit Exceeding ....................................................................................................................................................... 28
3.7.2
Locking Status ............................................................................................................................................................................... 28
3.7.3
Phase Lock Alarm (T0 only) .......................................................................................................................................................... 29
3.8
SELECTED INPUT CLOCK SWITCH ...........................................................................................................................................................30
3.8.1
Input Clock Validity ........................................................................................................................................................................ 30
3.8.2
Selected Input Clock Switch ......................................................................................................................................................... 30
3.8.2.1
Revertive Switch ............................................................................................................................................................... 30
3.8.2.2
Non-Revertive Switch (T0 only) ........................................................................................................................................ 31
3.8.3
Selected / Qualified Input Clocks Indication ................................................................................................................................ 31
3.9
SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE .......................................................................................................32
3.9.1
T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 32
3.9.2
T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 34
3.10 T0 / T4 DPLL OPERATING MODE ...............................................................................................................................................................35
3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 35
3.10.1.1 Free-Run Mode ................................................................................................................................................................ 35
3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 35
3.10.1.3 Locked Mode .................................................................................................................................................................... 35
Table of Contents
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| IDT82V3352 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SYNCHRONOUS ETHERNET WAN PLL |
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