參數(shù)資料
型號: IDT82V2052EPFG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 44/70頁
文件大?。?/td> 0K
描述: IC LIU E1 2CH SHORT HAUL 80-TQFP
標(biāo)準(zhǔn)包裝: 750
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 82V2052EPFG8
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
PROGRAMMING INFORMATION
49
December 12, 2005
4.3.10 COUNTER REGISTERS
Table-38 INTS1: Interrupt Status Register 1
(R, Address = 19H, 39H) (this register is reset and the relevant interrupt request is cleared after a read)
Symbol
Bit
Default
Description
DAC_OV_IS
7
0
This bit indicates the occurrence of the pulse amplitude overflow of Arbitrary Waveform Generator interrupt event
.
= 0: No pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred
= 1: The pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred
JAOV_IS
6
0
This bit indicates the occurrence of the Jitter Attenuator Overflow interrupt event.
= 0: No JA Overflow interrupt event occurred
= 1: JA Overflow interrupt event occurred
JAUD_IS
5
0
This bit indicates the occurrence of the Jitter Attenuator Underflow interrupt event.
= 0: No JA Underflow interrupt event occurred
= 1: JA Underflow interrupt event occurred
ERR_IS
4
0
This bit indicates the occurrence of the interrupt event generated by the detected PRBS logic error.
= 0: No PRBS logic error interrupt event occurred
= 1: PRBS logic error interrupt event occurred
EXZ_IS
3
0
This bit indicates the occurrence of the Excessive Zeros interrupt event.
= 0: No Excessive Zeros interrupt event occurred
= 1: EXZ interrupt event occurred
CV_IS
2
0
This bit indicates the occurrence of the Code Violation interrupt event.
= 0: No Code Violation interrupt event occurred
= 1: Code Violation interrupt event occurred
TMOV_IS
1
0
This bit indicates the occurrence of the One-Second Timer Expiration interrupt event.
= 0: No One-Second Timer Expiration interrupt event occurred
= 1: One-Second Timer Expiration interrupt event occurred
CNT_OV_IS
0
This bit indicates the occurrence of the Counter Overflow interrupt event.
= 0: No Counter Overflow interrupt event occurred
= 1: Counter Overflow interrupt event occurred
Table-39 CNT0: Error Counter L-byte Register 0
(R, Address = 1AH, 3AH)
Symbol
Bit
Default
Description
CNT_L[7:0]
7-0
00H
This register contains the lower eight bits of the 16-bit error counter. CNT_L[0] is the LSB.
Table-40 CNT1: Error Counter H-byte Register 1
(R, Address = 1BH, 3BH)
Symbol
Bit
Default
Description
CNT_H[7:0]
7-0
00H
This register contains the upper eight bits of the 16-bit error counter. CNT_H[7] is the MSB.
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