參數(shù)資料
型號: IDT82V2052EPFG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 18/70頁
文件大小: 0K
描述: IC LIU E1 2CH SHORT HAUL 80-TQFP
標(biāo)準(zhǔn)包裝: 750
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 82V2052EPFG8
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
25
December 12, 2005
3.5
LOS AND AIS DETECTION
3.5.1
LOS DETECTION
The Loss of Signal Detector monitors the amplitude of the incoming sig-
nal level and pulse density of the received signal on RTIPn and RRINGn.
LOS declare (LOS=1)
A LOS is detected when the incoming signal has “no transitions”, i.e.,
when the signal level is less than Q dB below nominal for N consecutive
pulse intervals. Here N is defined by LAC bit (MAINT0, 0CH...). LOS will be
declared by pulling LOSn pin to high (LOS=1) and LOS interrupt will be gen-
erated if it is not masked.
LOS clear (LOS=0)
The LOS is cleared when the incoming signal has “transitions”, i.e.,
when the signal level is greater than P dB below nominal and has an aver-
age pulse density of at least 12.5% for M consecutive pulse intervals, start-
ing with the receipt of a pulse. Here M is defined by LAC bit (MAINT0,
0CH...). LOS status is cleared by pulling LOSn pin to low.
Figure-11 LOS Declare and Clear
LOS detect level threshold
With the Adaptive Equalizer off, the amplitude threshold Q is fixed on
800 mVpp, while P=Q+200 mVpp (200 mVpp is the LOS level detect hys-
teresis).
With the Adaptive Equalizer on, the value of Q can be selected by
LOS[4:0] bit (RCF1, 0AH...), while P=Q+4 dB (4 dB is the LOS level detect
on page 42 for LOS[4:0] bit values available.
When the chip is configured by hardware, the Adaptive Equalizer can
not be enabled and Programmable LOS levels are not available (pin 58 &
pin 60 have to be set to ‘0’).
Criteria for declare and clear of a LOS detect
The detection supports G.775 and ETSI 300233/I.431. The criteria can
be selected by LAC bit (MAINT0, 0CH...).
Table-7 and Table-8 summarize LOS declare and clear criteria for both
with and without the Adaptive Equalizer enabled.
All Ones output during LOS
On the system side, the RDPn/RDNn will reflect the input pulse “transi-
tion” at the RTIPn/RRINGn side and output recovered clock (but the quality
of the output clock can not be guaranteed when the input level is lower than
the maximum receive sensitivity) when AISE bit (MAINT0, 0CH...) is 0; or
output All Ones as AIS when AISE bit (MAINT0, 0CH...) is 1. In this case
RCLKn output is replaced by MCLK.
On the line side, the TTIPn/TRINGn will output All Ones as AIS when
ATAO bit (MAINT0, 0CH...) is 1. The All Ones pattern uses MCLK as the
reference clock.
LOS indicator is always active for all kinds of loopback modes.
signal level<Q
(observing windows= N)
(observing windows= M)
signal level>P
density=OK
LOS=1
LOS=0
Table-7 LOS Declare and Clear Criteria, Adaptive Equalizer Disabled
Control bit (LAC)
LOS declare threshold
LOS clear threshold
0 = G.775
Level < 800 mVpp; N=32 bits
Level > 1 Vpp; M=32 bits; 12.5% mark density; <16 consecutive zeroes
1 = I.431/ETSI
Level < 800 mVpp; N=2048 bits
Level > 1 Vpp; M=32 bits; 12.5% mark density; <16 consecutive zeroes
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