參數(shù)資料
型號(hào)： IDT82V2052EPFG8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 24/70頁
文件大?。?/td> 0K
描述： IC LIU E1 2CH SHORT HAUL 80-TQFP
標(biāo)準(zhǔn)包裝： 750
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-TQFP（14x14）
包裝： 帶卷 (TR)
其它名稱： 82V2052EPFG8
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
30
December 12, 2005
3.8
ERROR DETECTION/COUNTING AND INSERTION
3.8.1
DEFINITION OF LINE CODING ERROR
The following line encoding errors can be detected and counted by the
IDT82V2052E:
Received Bipolar Violation (BPV) Error: In AMI coding, when two
consecutive pulses of the same polarity are received, a BPV error
is declared.
HDB3 Code Violation (CV) Error: In HDB3 coding, a CV error is
declared when two consecutive BPV errors are detected, and the
pulses that have the same polarity as the previous pulse are not the
HDB3 zero substitution pulses.
Excess Zero (EXZ) Error: There are two standards defining the
EXZ errors: ANSI and FCC. The EXZ_DEF bit (MAINT6, 12H...)
chooses which standard will be adopted by the corresponding
channel to judge the EXZ error. Table-11 shows definition of EXZ.
In hardware control mode, only ANSI standard is adopted.
3.8.2
ERROR DETECTION AND COUNTING
Which type of the receiving errors (Received CV/BPV errors, excess
zero errors and PRBS logic errors) will be counted is determined by
ERR_SEL[1:0] bits (MAINT6, 12H...). Only one type of receiving error can
be counted at a time except that when the ERR_SEL[1:0] bits are set to ‘11’,
both CV/BPV and EXZ errors will be detected and counted.
Theselectedtypeofreceivingerrorsiscountedinaninternal16-bitError
Counter. Once an error is detected, an error interrupt which is indicated by
corresponding bit in (INTS1, 19H...) will be generated if it is not masked.
This Error Counter can be operated in two modes: Auto Report Mode and
Manual Report Mode, as selected by the CNT_MD bit (MAINT6, 12H...).
In Single Rail mode, once BPV or CV errors are detected, the CVn pin will
be driven to high for one RCLK period.
Auto Report Mode
In Auto Report Mode, the internal counter starts to count the received
errors when the CNT_MD bit (MAINT6, 12H...) is set to ‘1’. A one-second
timer is used to set the counting period. The received errors are counted
within one second. If the one-second timer expires, the value in the internal
counter will be transferred to (CNT0, 1AH...) and (CNT1, 1BH...), then the
internal counter will be reset and start to count received errors for the next
second. The errors occurred during the transfer will be accumulated to the
next round. The expiration of the one-second timer will set TMOV_IS bit
(INTS1, 19H...) to ‘1’, and will generate an interrupt if the TIMER_IM bit
(INTM1,14H...)issetto‘0’.TheTMOV_ISbit(INTS1,19H...)willbecleared
after the interrupt register is read. The content in the (CNT0, 1AH...) and
(CNT1, 1BH...) should be read within the next second. If the counter over-
flows, a counter overflow interrupt which is indicated by CNT_OV_IS bit
(INTS1, 19H...) will be generated if it is not masked by CNT_IM bit (INTM1,
14H...).
Figure-15 Auto Report Mode
Manual Report Mode
In Manual Report Mode, the internal Error Counter starts to count the
received errors when the CNT_MD bit (MAINT6, 12H...) is set to ‘0’. When
there is a ‘0’ to ‘1’ transition on the CNT_TRF bit (MAINT6, 12H...), the data
inthecounterwillbetransferredto(CNT0,1AH...)and(CNT1,1BH...),then
the counter will be reset. The errors occurred during the transfer will be
accumulated to the next round. If the counter overflows, a counter overflow
interrupt indicated by CNT_OV_IS bit (INTS1, 19H...) will be generated if
it is not masked by CNT_IM bit (INTM1, 14H...).
Table-11 EXZ Definition
EXZ Definition
ANSI
FCC
AMI
More than 15 consecutive zeros are detected
More than 80 consecutive zeros are detected
HDB3
More than 3 consecutive zeros are detected
One-Second Timer expired?
counting
Auto Report Mode
(CNT_MD=1)
Bit TMOV_IS is set to '1'
Y
N
CNT0, CNT1
data in counter
counter
0
read the data in CNT0, CNT1 within
the next second
next second
repeats the
same process
Bit TMOV_IS is cleared after
the interrupt register is read
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