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參數(shù)資料
| 型號： | IDT82V2048SDAG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 60/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1 8CH SHORT 144-TQFP |
| 標準包裝： | 5,000 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2048SDAG |
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7
IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED
INDUSTRIAL TEMPERATURE RANGES
Hardware/Host Control Interface
MODE2
I
(Pulled to
VDDIO/2)
11
E2
MODE2: Control Mode Select 2
The signal on this pin determines which control mode is selected to control the device:
Hardware control pins include MODE[2:0], TS[2:0], LP[7:0], CODE, CLKE, JAS and OE.
Serial host Interface pins include CS, SCLK, SDI, SDO and INT.
Parallel host Interface pins include CS, A[4:0], D[7:0], WR/DS, RD/R/W, ALE/AS, INT and RDY/ACK. The
device supports multiple parallel host interface as follows (refer to MODE1 and MODE0 pin descriptions
below for details):
MODE1
I
43
K2
MODE1: Control Mode Select 1
In parallel host mode, the parallel interface operates with separate address bus and data bus when this pin
is low, and operates with multiplexed address and data bus when this pin is high.
In serial host mode or hardware mode, this pin should be grounded.
MODE0/CODE
I
88
H12
MODE0: Control Mode Select 0
In parallel host mode, the parallel host interface is configured for Motorola compatible hosts when this pin
is low, or for Intel compatible hosts when this pin is high.
CODE: Line Code Rule Select
In hardware control mode, the B8ZS (for T1 mode)/HDB3 (for E1 mode) encoder/decoder is enabled when
this pin is low, and AMI encoder/decoder is enabled when this pin is high. The selections affect all the
channels.
In serial host mode, this pin should be grounded.
CS/JAS
I
(Pulled to
VDDIO/2)
87
J11
CS: Chip Select (Active Low)
In host mode, this pin is asserted low by the host to enable host interface. A high to low transition must
occur on this pin for each read/write operation and the level must not return to high until the operation is
over.
JAS: Jitter Attenuator Select
In hardware control mode, this pin globally determines the Jitter Attenuator position:
Table-1 Pin Description (Continued)
Name
Type
Pin No.
Description
TQFP144 PBGA160
MODE2
Control Interface
Low
Hardware Mode
VDDIO/2
Serial Host Interface
High
Parallel Host Interface
MODE[2:0]
Host Interface
100
Non-multiplexed Motorola Mode Interface
101
Non-multiplexed Intel Mode Interface
110
Multiplexed Motorola Mode Interface
111
Multiplexed Intel Mode Interface
JAS
Jitter Attenuator (JA) Configuration
Low
JA in transmit path
VDDIO/2
JA not used
High
JA in receive path
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| IDT82V2051EPP8 | 功能描述:IC LIU E1 SGL SHORT HAUL 44-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2051EPPG | 功能描述:IC LIU E1 SGL SHORT HAUL 44-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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