參數(shù)資料
型號(hào)： IDT82V2048SDAG
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 45/62頁(yè)
文件大?。?/td> 0K
描述： IC LIU T1/E1 8CH SHORT 144-TQFP
標(biāo)準(zhǔn)包裝： 5,000
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
包裝： 托盤(pán)
其它名稱： 82V2048SDAG
5
IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED
INDUSTRIAL TEMPERATURE RANGES
Transmit and Receive Digital Data Interface
TD0/TDP0
TD1/TDP1
TD2/TDP2
TD3/TDP3
TD4/TDP4
TD5/TDP5
TD6/TDP6
TD7/TDP7
BPVI0/TDN0
BPVI1/TDN1
BPVI2/TDN2
BPVI3/TDN3
BPVI4/TDN4
BPVI5/TDN5
BPVI6/TDN6
BPVI7/TDN7
I
37
30
80
73
108
101
8
1
38
31
79
72
109
102
7
144
N2
L2
L13
N13
B13
D13
D2
B2
N3
L3
L12
N12
B12
D12
D3
B3
TDn: Transmit Data for Channel 0~7
When the device is in Single Rail mode, the NRZ data to be transmitted is input on this pin. Data on TDn is
sampled into the device on the falling edges of TCLKn, and encoded by AMI or B8ZS/HDB3 line code
rules before being transmitted to the line.
BPVIn: Bipolar Violation Insertion for Channel 0~7
Bipolar violation insertion is available in Single Rail mode 2 (see Table-2 on page 14 and Table-3 on page
14) with AMI enabled. A low-to-high transition on this pin will make the next logic one to be transmitted on
TDn the same polarity as the previous pulse, and violate the AMI rule. This is for testing.
TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~7
When the device is in Dual Rail Mode, the NRZ data to be transmitted for positive/negative pulse is input
on this pin. Data on TDPn/TDNn are sampled on the falling edges of TCLKn. The line code in dual rail
mode is as the follow:
Pulling pin TDNn high for more than 16 consecutive TCLK clock cycles will configure the corresponding
channel into Single Rail mode 1 (see Table-2 on page 14 and Table-3 on page 14).
TCLK0
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
I
36
29
81
74
107
100
9
2
N1
L1
L14
N14
B14
D14
D1
B1
TCLKn: Transmit Clock for Channel 0~7
The clock of 1.544 MHz (for T1 mode) or 2.048 MHz (for E1 mode) for transmit is input on this pin. The
transmit data at TDn/TDPn or TDNn is sampled into the device on the falling edges of TCLKn.
Pulling TCLKn high for more than 16 MCLK cycles, the corresponding transmitter is set in Transmit All
Ones (TAOS) state (when MCLK is clocked). In TAOS state, the TAOS generator adopts MCLK as the
clock reference.
If TCLKn is low, the corresponding transmit channel is set into power down state, while driver output ports
become high-Z.
Different combinations of TCLKn and MCLK result in different transmit mode. It is summarized as the fol-
lows:
Table-1 Pin Description (Continued)
Name
Type
Pin No.
Description
TQFP144 PBGA160
TDPn
TDNn
Output Pulse
0
Space
0
1
Negative Pulse
1
0
Positive Pulse
1
Space
MCLK
TCLKn
Transmit Mode
Clocked
Normal operation
Clocked
High (
≥ 16 MCLK)
Transmit All Ones (TAOS) signals to the line side in the corresponding
transmit channel.
Clocked
Low (
≥ 64 MCLK) The corresponding transmit channel is set into power down state.
High/Low TCLK1 is clocked
TCLKn is clocked Normal operation
TCLKn is high
(
≥ 16 TCLK1)
Transmit All Ones (TAOS) signals to the line side
in the corresponding transmit channel.
TCLKn is low
(
≥ 64 TCLK1)
Corresponding transmit channel is set into power
down state.
The receive path is not affected by the status of TCLK1. When MCLK
is high, all receive paths just slice the incoming data stream. When
MCLK is low, all the receive paths are powered down.
High/Low
TCLK1 is unavail-
able.
All eight transmitters (TTIPn & TRINGn) will be in high-Z.
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