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參數(shù)資料
| 型號： | IDT82V2048SDAG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 14/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1 8CH SHORT 144-TQFP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2048SDAG |
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IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION
INDUSTRIAL TEMPERATURE RANGES
2.9
POWER DRIVER FAILURE MONITOR
An internal power Driver Failure Monitor (DFMON), parallel
connected with TTIPn and TRINGn, can detect short circuit failure
between TTIPn and TRINGn pins. Bit SCPB in register GCF decides
whether the output driver short circuit protection is enabled. When the
short circuit protection is enabled, the driver output current is limited to a
typical value: 180 mAp. Also, register DF, DFI and DFM will be available.
When DFMON will detect a short circuit, register DF will be set. With a
short circuit failure detected and short circuit protection enabled, register
DFI will be set and an interrupt will be generated on pin INT.
2.10 TRANSMIT LINE SIDE SHORT CIRCUIT FAILURE
DETECTION
In E1 or T1 with 5 V VDDT, a pair of 9.5 serial resistors connect
with TTIPn and TRINGn pins and limit the output current. In this case,
the output current is a limited value which is always lower than the
typical line short circuit current 180 mAp, even if the transmit line side is
shorted.
Refer to Table-12 External Components Values for details.
2.11 LINE PROTECTION
In transmit side, the Schottky diodes D1~D4 are required to protect
the line driver and improve the design robustness. For differential
receive interface and single ended receive interface, the line protection
in receive side is different. To protect the receiver against current surges
coupled in the device, two series resistors of 1 k are used for differen-
tial receive interface and a series resistor of 1 k is used for single
resistor/resistors does/do not affect the receiver sensitivity, since the
receiver impedance is as high as 120 k typically.
2.12 HITLESS PROTECTION SWITCHING (HPS)
The IDT82V2048S transceivers include an output driver with high-Z
feature for T1/E1 redundancy applications. This feature reduces the cost
of redundancy protection by eliminating external relays. Details of HPS
are described in relative Application Note.
2.13 SOFTWARE RESET
Writing register RS will cause software reset by initiating about 1 s
reset cycle. This operation set all the registers to their default value.
2.14 POWER ON RESET
During power up, an internal reset signal sets all the registers to
default values. The power-on reset takes at least 10 s, starting from
when the power supply exceeds 2/3 VDDA.
2.15 POWER DOWN
Each transmit channel will be powered down by pulling pin TCLKn
low for more than 64 MCLK cycles (if MCLK is available) or about 30 s
(if MCLK is not available). In host mode, each transmit channel will also
be powered down by setting bit TPDNn in register e-TPDN to ‘1’.
All the receivers will be powered down when MCLK is low. When
MCLK is clocked or high, setting bit RPDNn in register e-RPDN to ‘1’ will
configure the corresponding receiver to be powered down.
2.16 INTERFACE WITH 5 V LOGIC
The IDT82V2048S can interface directly with 5 V TTL family devices.
The internal input pads are tolerant to 5 V output from TTL and CMOS
family devices.
2.17 LOOPBACK MODE
The device provides five different diagnostic loopback configurations:
Digital Loopback, Analog Loopback, Remote Loopback, Dual Loopback
and Inband Loopback. In host mode, these functions are implemented
by programming the registers DLB, ALB, RLB and Inband Loopback
register group respectively. In hardware mode, only Analog Loopback
and Remote Loopback can be selected by pin LPn.
2.17.1 DIGITAL LOOPBACK
By programming the bits of register DLB, each channel of the device
can be configured in Local Digital Loopback. In this configuration, the
data and clock to be transmitted, after passing the encoder, are looped
back to Jitter Attenuator (if enabled) and decoder in the receive path,
then output on RCLKn, RDn/RDPn and CVn/RDNn. The data to be
transmitted are still output on TTIPn and TRINGn while the data
received on RTIPn and RRINGn are ignored. The Loss Detector is still in
use. Figure-14 shows the process.
During Digital Loopback, the received signal on the receive line is still
monitored by the LOS Detector (See 2.4.5 Loss of Signal (LOS) Detec-
tion for details). In case of a LOS condition and AIS insertion enabled, all
ones signal will be output on RDPn/RDNn. With ATAO enabled, all ones
signal will be also output on TTIPn/TRINGn. AIS insertion can be
enabled by setting AISE bit in register GCF and ATAO can be enabled
by setting register ATAO (default disabled).
2.17.2 ANALOG LOOPBACK
By programming the bits of register ALB or pulling pin LPn high,
each channel of the device can be configured in Analog Loopback. In
this configuration, the data to be transmitted output from the line driver
are internally looped back to the slicer and peak detector in the receive
path and output on RCLKn, RDn/RDPn and CVn/RDNn. The data to be
transmitted are still output on TTIPn and TRINGn while the data
received on RTIPn and RRINGn are ignored. The LOS Detector (See
2.4.5 Loss of Signal (LOS) Detection for details) is still in use and moni-
tors the internal looped back data. If a LOS condition on TDPn/TDNn is
expected during Analog Loopback, ATAO should be disabled (default).
Figure-15 shows the process.
The TTIPn and RTIPn, TRINGn and RRINGn cannot be connected
directly to do the external analog loopback test. Line impedance loading
is required to conduct the external analog loopback test.
2.17.3 REMOTE LOOPBACK
By programming the bits of register RLB or pulling pin LPn low, each
channel of the device can be set in Remote Loopback. In this configura-
tion, the data and clock recovered by the clock and data recovery
circuits are looped to waveform shaper and output on TTIPn and
TRINGn. The jitter attenuator is also included in loopback when enabled
in the transmit or receive path. The received data and clock are still
output on RCLKn, RDn/RDPn and CVn/RDNn while the data to be trans-
mitted on TCLKn, TDn/TDPn and BPVIn/TDNn are ignored. The LOs
Detector is still in use. Figure-16 shows the process.
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