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參數(shù)資料
| 型號： | IDT82V2048SDAG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 36/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1 8CH SHORT 144-TQFP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2048SDAG |
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41
IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION
INDUSTRIAL TEMPERATURE RANGES
4.2
JTAG DATA REGISTER
4.2.1
DEVICE IDENTIFICATION REGISTER (IDR)
The IDR can be set to define the producer number, part number and
the device revision, which can be used to verify the proper version or
revision number that has been used in the system under test. The IDR is
32 bits long and is partitioned as in Table-20. Data from the IDR is
shifted out to TDO LSB first.
4.2.2
BYPASS REGISTER (BR)
The BR consists of a single bit. It can provide a serial path between
the TDI input and TDO output, bypassing the BSR to reduce test access
times.
4.2.3
BOUNDARY SCAN REGISTER (BSR)
The BSR can apply and read test patterns in parallel to or from all the
digital I/O pins. The BSR is a 98 bits long shift register and is initialized
and read using the instruction EXTEST or SAMPLE/PRELOAD. Each
pin is related to one or more bits in the BSR. Please refer to Table-21 for
details of BSR bits and their functions.
Table-19 Instruction Register Description
IR Code
Instruction
Comments
000
Extest
The external test instruction allows testing of the interconnection to other devices. When the current instruction is the
EXTEST instruction, the boundary scan register is placed between TDI and TDO. The signal on the input pins can be
sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by
shifting the boundary scan register using the Shift-DR state. The signal on the output pins can be controlled by loading
patterns shifted in through input TDI into the boundary scan register using the Update-DR state.
100
Sample/Preload
The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed
between TDI and TDO. The normal path between IDT82V2048S logic and the I/O pins is maintained. Primary device
inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled val-
ues can then be viewed by shifting the boundary scan register using the Shift-DR state.
110
Idcode
The identification instruction is used to connect the identification register between TDI and TDO. The device's identifica-
tion code can then be shifted out using the Shift-DR state.
111
Bypass
The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay. The instruction is used
to bypass the device.
Table-20 Device Identification Register Description
Bit No.
Comments
0Set to ‘1’
1~11
Producer Number
12~27
Part Number
28~31
Device Revision
Table-21 Boundary Scan Register Description
Bit No.
Bit Symbol
Pin Signal
Type
Comments
0POUT0
LP0
I/O
1PIN0
LP0
I/O
2POUT1
LP1
I/O
3PIN1
LP1
I/O
4POUT2
LP2
I/O
5PIN2
LP2
I/O
6POUT3
LP3
I/O
7PIN3
LP3
I/O
8POUT4
LP4
I/O
9PIN4
LP4
I/O
10
POUT5
LP5
I/O
11
PIN5
LP5
I/O
12
POUT6
LP6
I/O
13
PIN6
LP6
I/O
14
POUT7
LP7
I/O
15
PIN7
LP7
I/O
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