參數(shù)資料
型號(hào)： IDT82V2042EPF8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 44/83頁(yè)
文件大?。?/td> 0K
描述： IC LIU T1/J1/E1 2CH SHORT 80TQFP
標(biāo)準(zhǔn)包裝： 750
類(lèi)型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-TQFP（14x14）
包裝： 帶卷 (TR)
其它名稱(chēng)： 82V2042EPF8
IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
PROGRAMMING INFORMATION
49
December 12, 2005
4.3.6
NETWORK DIAGNOSTICS CONTROL REGISTERS
Table-34 RCF2: Receiver Configuration Register 2
(R/W, Address = 0BH, 2BH)
Symbol
Bit
Default
Description
-
7-6
00
Reserved.
SLICE[1:0]
5-4
01
Receive slicer threshold
= 00: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 40% of the peak amplitude.
= 01: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 50% of the peak amplitude.
= 10: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 60% of the peak amplitude.
= 11: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 70% of the peak amplitude.
-
3-2
10
Reserved
MG[1:0]
1-0
00
Monitor gain setting: these bits select the internal linear gain boost
= 00: 0 dB
= 01: 22 dB
= 10: 26 dB
= 11: 32 dB
Table-35 MAINT0: Maintenance Function Control Register 0
(R/W, Address = 0CH, 2CH)
Symbol
Bit
Default
Description
-
7
0
Reserved.
PATT[1:0]
6-5
00
These bits select the internal pattern and insert it into transmit data stream.
= 00: Normal operation (PATT_CLK = 0) / insert all zeros (PATT_CLK = 1)
= 01: Insert All Ones
= 10: Insert PRBS (E1: 215-1) or QRSS (T1/J1: 220-1)
= 11: Insert programmable Inband loopback activate or deactivate code (default value 00001)
PATT_CLK
4
0
Selects reference clock for transmitting internal pattern
= 0: Uses TCLKn as the reference clock
= 1: Uses MCLK as the reference clock
PRBS_INV
3
0
Inverts PRBS
= 0: The PRBS data is not inverted
= 1: The PRBS data is inverted before transmission and detection
LAC
2
0
LOS/AIS criterion is selected as below:
= 0: G.775 (E1) / T1.231 (T1/J1)
= 1: ETSI 300233& I.431 (E1) / I.431 (T1/J1)
AISE
1
0
AIS enable during LOS
= 0: AIS insertion on RDPn/RDNn/RCLKn is disabled during LOS
= 1: AIS insertion on RDPn/RDNn/RCLKn is enabled during LOS
ATAO
0
Automatically Transmit All Ones (enabled only when PATT[1:0] = 00)
= 0: Disabled
= 1: Automatically Transmit All Ones pattern at TTIPn/TRINGn during LOS
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IDT82V2044 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
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IDT82V2044BBG 功能描述:IC LIU T1/E1 QUAD SHORT 160-BGA RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
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