參數(shù)資料
型號(hào)： IDT82V2042EPF8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 19/83頁(yè)
文件大?。?/td> 0K
描述： IC LIU T1/J1/E1 2CH SHORT 80TQFP
標(biāo)準(zhǔn)包裝： 750
類(lèi)型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-TQFP（14x14）
包裝： 帶卷 (TR)
其它名稱(chēng)： 82V2042EPF8
IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
26
December 12, 2005
3.4.3
ADAPTIVE EQUALIZER
The Adaptive Equalizer can be enabled to increase the receive sensi-
tivity and to allow programming of the LOS level up to -24 dB. See section
3.6 LOS AND AIS DETECTION. It can be enabled or disabled by setting
EQ_ON bit to ‘1’ or ‘0’ (RCF1, 0AH...).
3.4.4
RECEIVE SENSITIVITY
In Host mode, the Receive Sensitivity for both E1 and T1/J1 is -10 dB.
With the Adaptive Equalizer enabled, the receive sensitivity will be -20 dB.
In Hardware mode, the Adaptive Equalizer can not be enabled and the
receive sensitivity is fixed at -10 dB for both E1 and T1/J1. Refer to 5 HARD-
for details.
3.4.5
DATA SLICER
The Data Slicer is used to generate a standard amplitude mark or a
space according to the amplitude of the input signals. The threshold can
be 40%, 50%, 60% or 70%, as selected by the SLICE[1:0] bits (RCF2,
0BH...). The output ofthe Data Slicer is forwardedto theCDR(Clock &Data
Recovery) unit or to the RDPn/RDNn pins directly if the CDR is disabled.
3.4.6
CDR (Clock & Data Recovery)
The CDR is used to recover the clock and data from the received signal.
The recovered clock tracks the jitter in the data output from the Data Slicer
and keeps the phase relationship between data and clock during the
absence of the incoming pulse. The CDR can also be by-passed in the Dual
Rail mode. When CDR is by-passed, the data from the Data Slicer is output
to the RDPn/RDNn pins directly.
3.4.7
DECODER
In T1/J1 applications, the R_MD[1:0] bits (RCF0, 09H...) is used to
selecttheAMIdecoderorB8ZSdecoder.InE1applications,theR_MD[1:0]
bits (RCF0, 09H...) are used to select the AMI decoder or HDB3 decoder.
When the chipis configured by hardware, theoperation mode of receive
and transmit path can be selected by setting RXTXM[1:0] pins on a global
basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.4.8
RECEIVE PATH SYSTEM INTERFACE
The receive path system interface consists of RCLKn pin, RDn/RDPn
pin and RDNn pin. In E1 mode, the RCLKn outputs a recovered 2.048 MHz
clock.InT1/J1mode,theRCLKnoutputsarecovered1.544MHzclock.The
received data is updated on the RDn/RDPn and RDNn pins on the active
edge of RCLKn. The active edge of RCLKn can be selected by the
RCLK_SEL bit (RCF0, 09H...). And the active level of the data on RDn/
RDPn and RDNn can be selected by the RD_INV bit (RCF0, 09H...).
In hardware control mode, only the active edge of RCLKn can be
selected.IfRCLKEissettohigh,thefallingedgewillbechosenastheactive
edge of RCLKn. If RCLKE is set to low, the rising edge will be chosen as
the active edge of RCLKn. The active level of the data on RDn/RDPn and
RDNn is the same as that in software control mode.
Thereceiveddatacanbeoutputtothesystemsideintwodifferentways:
Single Rail or Dual Rail, as selected by R_MD bit [1] (RCF0, 09H...). In Sin-
gle Rail mode, only RDn pin is used to output data and the RDNn/CVn pin
is used to report the received errors. In Dual Rail Mode, both RDPn pin and
RDNn pin are used for outputting data.
In the receive Dual Rail mode, the CDR unit can be by-passed by setting
R_MD[1:0] to ‘11’ (binary). In this situation, the output data from the Data
Slicer will be output to the RDPn/RDNn pins directly, and the RCLKn out-
puts the exclusive OR (XOR)of the RDPn andRDNn. Thisis calledreceiver
slicer mode. In this case, the transmit path is still operating in Dual Rail
mode.
3.4.9
RECEIVE PATH POWER DOWN
The receive path can be powered down individually by setting R_OFF
bit (RCF0, 09H...) to ‘1’. In this case, the RCLKn, RDn/RDPn, RDNn and
LOSn will be logic low.
In hardware control mode, receiverpower down can be selected by pull-
ing RPDn pin to high on a per channel basis. Refer to 5 HARDWARE CON-
for more details.
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