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| 型號： | IDT82V2042EPF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 16/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/J1/E1 2CH SHORT 80TQFP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 82V2042EPF8 |
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IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
23
December 12, 2005
3.3.4
TRANSMIT PATH LINE INTERFACE
The transmit line interface consists of TTIPn and TRINGn pins. The
impedance matching can be realized by the internal impedance matching
circuit or the external impedance matching circuit. If T_TERM[2] is set to
‘0’, the internal impedance matching circuit will be selected. In this case,
the T_TERM[1:0] bits (TERM, 02H...) can be set to choose 75
, 100 ,
110
or 120 internal impedance of TTIPn/TRINGn. If T_TERM[2] is set
to ‘1’, the internal impedance matching circuit will be disabled. In this case,
the external impedance matching circuit will be used to realize the imped-
ance matching. For T1/J1 mode, the external impedance matching circuit
for the transmitter is not supported.
Figure-8 shows the appropriate external components to connect with
the cable for one channel. Table-10 is the list of the recommended imped-
ance matching for transmitter.
In hardware control mode, TERMn pin can be used to select impedance
matchingforbothreceiverandtransmitteronaperchannelbasis.IfTERMn
pin is low, internal impedance network will be used. If TERMn pin is high,
external impedance network will be used in E1 mode, or external imped-
ance network for receiver and internal impedance network for transmitter
will be used in T1/J1 mode. (This applies to ZB die revision only). When
internal impedance network is used, PULSn[3:0] pins should be set to
select the specific internal impedance in the corresponding channel. Refer
to 5 HARDWARE CONTROL PIN SUMMARY for details.
The TTIPn/TRINGn can also be turned into high impedance globally by
pulling THZ pin to high or individually by setting the THZ bit (TCF1, 05H...)
to ‘1’. In this state, the internal transmit circuits are still active.
In hardware control mode, TTIPn/TRINGn pins can be turned into high
impedance globally by pulling THZ pin to high. Refer to 5 HARDWARE CON-
for details.
Besides, in the following cases, TTIPn/TRINGn will also become high
impedance:
Loss of MCLK;
Loss of TCLKn (exceptions: Remote Loopback; Transmit internal
pattern by MCLK);
Transmit path power down;
After software reset; pin reset and power on.
Note: The precision of the resistors should be better than ± 1%
3.3.5
TRANSMIT PATH POWER DOWN
The transmit path can be powered down individually by setting the
T_OFF bit (TCF0, 04H...) to ‘1’. In this case, the TTIPn/TRINGn pins are
turned into high impedance.
In hardware control mode, the transmit path can be powered down by
setting PATTn[1:0] pins to ‘11’ on a per channel basis. Refer to 5 HARD-
for details.
Table-9 Transmit Waveform Value For J1 0~655 ft
Sample
UI 1
UI 2
UI 3
UI 4
1
0010111
1000010
0000000
2
0100111
1000001
0000000
3
0100111
0000000
4
0100110
0000000
5
0100101
0000000
6
0100101
0000000
7
0100101
0000000
8
0100100
0000000
9
0100011
0000000
10
1001010
0000000
11
1001010
0000000
12
1001001
0000000
13
1000111
0000000
14
1000101
0000000
15
1000100
0000000
16
1000011
0000000
SCAL[5:0] = 110110 (default), One step change of this value of SCAL[5:0]
results in 2% scaling up/down against the pulse amplitude.
Table-10 Impedance Matching for Transmitter
Cable Configuration
Internal Termination
External Termination
T_TERM[2:0]
PULS[3:0]
RT
T_TERM[2:0]
PULS[3:0]
RT
E1/75
000
0000
0
1XX
0001
9.4
E1/120
001
0001
T1/0~133 ft
010
0010
-
T1/133~266 ft
0011
T1/266~399 ft
0100
T1/399~533 ft
0101
T1/533~655 ft
0110
J1/0~655 ft
011
0111
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