參數(shù)資料
型號: IDT82P2916BFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 99/138頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 16CH SH 484BGA
標準包裝: 84
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 16
電源電壓: 1.8V, 3.3V
功率(瓦特): 3.10W
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 484-LFBGA
供應商設備封裝: 484-CABGA(19x19)
包裝: 托盤
包括: AIS 警報檢測器和發(fā)生器,回送功能,PRBS 發(fā)生器 / 檢測器,遠程檢測器和發(fā)生器
IDT82P2916
16-CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Miscellaneous
63
April 24, 2010
4.1.1
POWER-ON RESET
Power-on reset is initiated during power-up. When all VDD inputs
(1.8V and 3.3V) reach approximately 60% of the standard value of VDD,
power-on reset begins. If MCLK is applied, power-on reset will complete
within 1 ms maximum; if MCLK is not applied, the device remains in
reset state.
4.1.2
HARDWARE RESET
Pulling the RST pin to low will initiate hardware reset. The reset cycle
should be more than 1 s. If the RST pin is held low continuously, the
device remains in reset state.
4.1.3
GLOBAL SOFTWARE RESET
Writing the RST register will initiate global software reset. Once initi-
ated, global software reset completes in 1 s maximum.
4.1.4
PER-CHANNEL SOFTWARE RESET
Writing a ‘1’ to the CHRST bit (b1, CHCF,...) will initiate per-channel
software reset. Once initiated, per-channel software reset completes in 1
s maximum and the CHRST bit (b1, CHCF,...) is self cleared.
This reset is different from other resets, for:
It does not reset the T1E1 bit (b0, CHCF,...). That is, the operation
mode of each channel is not changed;
It does not reset the global registers, state machines and common
pins (including the pins of clock generator, microprocessor inter-
face and JTAG interface);
It does not reset the other channels.
4.2
MICROPROCESSOR INTERFACE
The microprocessor interface provides access to read and write the
registers in the device. The interface consists of:
Serial microprocessor interface;
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