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參數(shù)資料
| 型號(hào)： | IDT82P2816BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 69/146頁(yè) |
| 文件大小： | 0K |
| 描述： | IC LIU T1/J1/E1 16+1CH 416-PBGA |
| 標(biāo)準(zhǔn)包裝： | 5 |
| 功能： | 線路接口單元（LIU） |
| 接口： | E1，J1，T1 |
| 電路數(shù)： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 416-BGA |
| 供應(yīng)商設(shè)備封裝： | 416-PBGA（27x27） |
| 包裝： | 托盤 |
| 包括： | 缺陷和警報(bào)檢測(cè)，驅(qū)動(dòng)器過流檢測(cè)和保護(hù)，LLOS 檢測(cè)，PRBSARB / IB 檢測(cè)和生成 |
| 其它名稱： | 82P2816BB |
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IDT82P2816
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Functional Description
29
February 6, 2009
3.2.7
RECEIVER POWER DOWN
Set the R_OFF bit (b5, RCF0,...) to ‘1’ will power down the corre-
sponding receiver.
In this way, the corresponding receive circuit is turned off and the
RTIPn/RRINGn pins are forced to High-Z state. The pins on receive
system interface (including RDn/RDPn, RDNn/RMFn, RCLKn/RMFn)
will be in High-Z state if the RHZ bit (b6, RCF0,...) is ‘1’ or in low level if
the RHZ bit (b6, RCF0,...) is ‘0’.
After clearing the R_OFF bit (b5, RCF0,...), it will take 1 ms for the
receiver to achieve steady state, i.e., to return to the previous configura-
tion and performance.
3.3
TRANSMIT PATH
3.3.1
TRANSMIT SYSTEM INTERFACE
The data from the system side is input to the device in three modes:
Single Rail NRZ Format mode, Dual Rail NRZ Format mode and Dual
Rail RZ Format mode, as selected by the T_MD[1:0] bits (b1~0,
If data is input on TDn in NRZ format and a 1.544 MHz (in T1/J1
mode) or 2.048 MHz (in E1 mode) clock is input on TCLKn, the transmit
system interface is in Single Rail NRZ Format mode. In this mode, the
data is encoded and sampled on the active edge of TCLKn. TMFn is
updated on the active edge of TCLKn and can be selected to indicate
PRBS/ARB, SAIS, TOC, TLOS or SEXZ. Refer to Section 3.5.7.2 TMFn
Indication for the description of TMFn.
If data is input on TDPn and TDNn in NRZ format and a 1.544 MHz
(in T1/J1 mode) or 2.048 MHz (in E1 mode) clock is input on TCLKn, the
transmit system interface is in Dual Rail NRZ Format mode. In this
mode, the data is pre-encoded and sampled on the active edge of
TCLKn.
If data is input on TDPn and TDNn in RZ format and no transmit
clock is input, the transmit system interface is in Dual Rail RZ Format
mode. In this mode, the data is pre-encoded. TMFn can be selected to
indicate PRBS/ARB, SAIS, TOC, TLOS, SEXZ, SBPV, SEXZ + SBPV or
SLOS. Refer to Section 3.5.7.2 TMFn Indication for the description of
TMFn. The Tx Clock Recovery block is used to recover the clock signal
from the data input on TDPn and TDNn. Refer to Section 3.3.2 Tx Clock
Table-4 summarizes the multiplex pin used in different transmit
system interface.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82P2816BBG | 功能描述:IC LINE INTERFACE UNIT 416-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| IDT82P2821 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:21(+1) Channel High-Density T1/E1/J1 Line Interface Unit |
| IDT82P2821BH | 功能描述:IC LIU T1/J1/E1 21+1CH 640-PBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| IDT82P2821BHG | 功能描述:IC LINE INTERFACE UNIT 640-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| IDT82P2828 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:28(+1) Channel High-Density T1/E1/J1 Line Interface Unit |
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