參數(shù)資料
型號: IDT82P2816BB
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 57/146頁
文件大?。?/td> 0K
描述: IC LIU T1/J1/E1 16+1CH 416-PBGA
標(biāo)準(zhǔn)包裝: 5
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 1
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 416-BGA
供應(yīng)商設(shè)備封裝: 416-PBGA(27x27)
包裝: 托盤
包括: 缺陷和警報檢測,驅(qū)動器過流檢測和保護,LLOS 檢測,PRBSARB / IB 檢測和生成
其它名稱: 82P2816BB
IDT82P2816
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Pin Description
18
February 6, 2009
Clock
MCLK
Input
AF21
MCLK: Master Clock Input
MCLK provides a stable reference timing for the IDT82P2816. MCLK should be a clock with +/
-32 ppm (in T1/J1 mode) or +/-50 ppm (in E1 mode) accuracy. The clock frequency of MCLK
is informed to the device by MCKSEL[3:0].
If MCLK misses (duty cycle is less than 30% for 10 s) and then recovers, the device will be
reset automatically.
MCKSEL[0]
MCKSEL[1]
MCKSEL[2]
MCKSEL[3]
Input
AE21
AD21
AD22
AC22
MCKSEL[3:0]: Master Clock Selection
These four pins inform the device of the clock frequency input on MCLK:
CLKT1
Output
AC21
CLKT1: 8 KHz / T1 Clock Output
The output on CLKT1 can be enabled or disabled, as determined by the CLKT1_EN bit (b1,
When the output is enabled, CLKT1 outputs an 8 KHz or 1.544 MHz clock, as selected by the
CLKT1 bit (b0, CLKG). The output is locked to MCLK.
When the output is disabled, CLKT1 is in High-Z state.
CLKE1
Output
AD20
CLKE1: 8 KHz / E1 Clock Output
The output on CLKE1 can be enabled or disabled, as determined by the CLKE1_EN bit (b3,
When the output is enabled, CLKE1 outputs an 8 KHz or 2.048 MHz clock, as selected by the
CLKE1 bit (b2, CLKG). The output is locked to MCLK.
When the output is disabled, CLKE1 is in High-Z state.
Name
I / O
Pin No.
Description
MCKSEL[3:0]*
Frequency (MHz)
0000
1.544
0001
1.544 X 2
0010
1.544 X 3
0011
1.544 X 4
0100
1.544 X 5
0101
1.544 X 6
0110
1.544 X 7
0111
1.544 X 8
1000
2.048
1001
2.048 X 2
1010
2.048 X 3
1011
2.048 X 4
1100
2.048 X 5
1101
2.048 X 6
1110
2.048 X 7
1111
2.048 X 8
Note:
0: GNDD
1: VDDIO
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