參數(shù)資料
型號: IDT79RC32K438-300BB
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 56/59頁
文件大?。?/td> 0K
描述: IC MPU 32BIT CORE 300MHZ 416-BGA
標(biāo)準(zhǔn)包裝: 40
系列: Interprise™
處理器類型: MIPS32 32-位
速度: 300MHz
電壓: 1.3V
安裝類型: 表面貼裝
封裝/外殼: 416-BGA
供應(yīng)商設(shè)備封裝: 416-PBGA(27x27)
包裝: 托盤
其它名稱: 79RC32K438-300BB
6 of 59
May 25, 2004
IDT 79RC32438
DDRVREF
I
DDR Voltage Reference. SSTL_2 DDR voltage reference generated by an
external source.
DDRWEN
O
DDR Write Enable. DDR write enable is asserted during DDR write transac-
tions.
PCI Bus
PCIAD[31:0]
I/O
PCI Multiplexed Address/Data Bus. Address is driven by a bus master during
initial PCIFRAMEN assertion. Data is then driven by the bus master during
writes or by the bus target during reads.
PCICBEN[3:0]
I/O
PCI Multiplexed Command/Byte Enable Bus. PCI command is driven by the
bus master during the initial PCIFRAMEN assertion. Byte enable signals are
driven by the bus master during subsequent data phase(s).
PCICLK
I
PCI Clock. Clock used for all PCI bus transactions.
PCIDEVSELN
I/O
PCI Device Select. This signal is driven by a bus target to indicate that the tar-
get has decoded the address as one of its own address spaces.
PCIFRAMEN
I/O
PCI Frame. Driven by a bus master. Assertion indicates the beginning of a bus
transaction. Negation indicates the last data.
PCIGNTN[3:0]
I/O
PCI Bus Grant.
In PCI host mode with internal arbiter:
The assertion of these signals indicates to the agent that the internal RC32438
arbiter has granted the agent access to the PCI bus.
In PCI host mode with external arbiter:
PCIGNTN[0]: asserted by an external arbiter to indicate to the RC32438 that
access to the PCI bus has been granted.
PCIGNTN[3:1]: unused and driven high.
In PCI satellite mode:
PCIGNTN[0]: This signal is asserted by an external arbiter to indicate to the
RC32438 that access to the PCI bus has been granted.
PCIGNTN[1]: this signal takes on the alternate function of PCIEECS and is used
as a PCI Serial EEPROM chip select
PCIGNTN[3:2]: unused and driven high.
Note: When the GPIO register is programmed in the alternate function mode for
bits GPIO [26] and [28], these bits become PCIGNTN [4] and [5] respectively.
PCIIRDYN
I/O
PCI Initiator Ready. Driven by the bus master to indicate that the current datum
can complete.
PCILOCKN
I/O
PCI Lock. This signal is asserted by an external bus master to indicate that an
exclusive operation is occurring.
PCIPAR
I/O
PCI Parity. Even parity of the PCIAD[31:0] bus. Driven by the bus master during
address and write Data phases. Driven by the bus target during the read data
phase.
PCIPERRN
I/O
PCI Parity Error. If a parity error is detected, this signal is asserted by the
receiving bus agent 2 clocks after the data is received.
Signal
Type
Name/Description
Table 1 Pin Description (Part 3 of 9)
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