參數(shù)資料
型號(hào)： IDT77155
廠商： Integrated Device Technology, Inc.
英文描述： PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
中文描述： 物理層（增距鏡TC - PMD）的用戶網(wǎng)絡(luò)接口的155Mbps的ATM網(wǎng)絡(luò)中的應(yīng)用
文件頁(yè)數(shù)： 5/50頁(yè)
文件大?。?/td> 307K
代理商： IDT77155
IIDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
8.03
5
Symbol
RBYP
Name
Receive Bypass
I/O
I
Description
Active high RBYP input disables clock recovery. If enabled, the receive different serial data
RXD+/- is sampled on the rising edged of the receive differential reference clock RRCLK+/-.
If RBYP is disabled, the receive clocks are recovered from RXD+/- bit stream. RBYP has an
integral pull down resistor.
Pin #: 41
This signal is asserted to indicate either 0 or a maximum of 4 morebytes are present in the
tristate receive FIFO. The indication of the receive FIFO level is programmable, as is the
polarity of this signal. Signal is updated on the rising edge of RFCLK. The RCA signal is
tristated in UTOPIA level-2 mode (MPHYEN asserted) and driven as per the multi-phy
protocol.
Pin #: 69
Provides a timing reference, and is a divide-by-8 version of tri-covered clock when RBYP is
disabled or RRCLK+/- when RBYP is enabled.
Pin #: 57
Receive GFC pulse indicates the start of the four generic flow control bits (GFC) in the
RGFC Pulse output. RCP is coincident with the most significant GFC bits. RCP is updated
on the rising edge of RCLK.
Pin #: 60
Active low read signal to read contents of addressed register. The data bus is driven by the
contents of the addresses register when the read signal is asserted along with the chip
select (CS) signal.
Pin #: 105
The receive cell data to the ATM layer from the receive FIFO. This is updated on the rising
edge of RFCLK. RDAT[7:0] is tristated if TSEN is asserted or if MPHYEN is asserted. In
UTOPIA single-phy mode, it is driven if RRDENB is asserted (TSEN also asserted) or
always driven if TSEN is low. In UTOPIA multi-phy mode, RDAT[7:0] is driven following the
level-2 protocol.
Pin #: RDAT0/70, RDAT1/71, RDAT2/74, RDAT3/75, RDAT4/76, RDAT5/77, RDAT6/78,
RDAT7/79
The receive ATM clock from the ATM layer <= 40 MHz. The start of cell indication, the
transmit data, and the transmit data parity signals are updated on the rising edge of this
clock. RRDENB is sampled on the rising edge of this clock.
Pin #: 67
An 8 KHz signal synchronized to RCLK. It is pulse high for one clock every 2430 RCLK
cycles for STS-3c or every 810 RCLK cycles for STS-1. It is updated on the rising edge of
RCLK.
Pin #: 58
Outputs the extracted generic flow control bits (GFC) in a serial stream. The four GFC bits
are output for each receive cell, and the first of the four bits is coincident with the RCP
output, RGFC is low until cell delineation is achieved. RGFC is updated on the rising edge of
RCLK.
Pin #: 59
Inputs contain a jitter-free 19.44 MHz or a 6.48 MHz reference clock when clock recovery
is enabled (RBYP = 0). When RBYP is enabled, RRCLK+/- is nominally a 155.52 MHz or
51.84 MHz 50% duty cycle clock and provides the timing for the internal receive functions.
RXD+/- is sampled on the rising edge of RRCLK+/-
Pin #: RRCLK+/34/ RRCLK-/33
Active low signal from ATM signifying that data will be sampled on RDAT[7:0] in the
following clock cycle. When sampled high, RSOC and RDAT[7:0] are tristated, if TSEN is
enabled. RRDENB must operate with RFCLK at high rate to prevent receive FIFO overflow
and loss of receive data.
Pin #: 68
RCA/
RXEMPTY
Receive Cell
Available
O
RCLK
Receive Clock
O
RCP
Receive Cell
O
RD
Read
I
RDAT0-
RDAT7
Receive Data
O
RFCLK
Receive FIFO
Clock
I
RFP
Receive Frame
Pulse
O
RGFC
Receive Generic
Flow Control
O
RRCLK+
RRCLK-
Receive Differential
I
Reference Clock
RRDENB
Receive Read
Enable
I
PIN DESCRIPTIONS (CONTINUED)
相關(guān)PDF資料
PDF描述
IDT77155L155PX PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
IDT77301 UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
IDT77301L12PF UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
IDT77301L12PFI UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
IDT77305 UTOPIAFIFO 4 PORT MULTIPLEXER FIFO
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT77155L155PX 制造商:INT_DEV_TECH 功能描述:
IDT77201L25PF 制造商:Integrated Device Technology Inc 功能描述:
IDT77211L155PQF 制造商:Integrated Device Technology Inc 功能描述:ATM/SONET SEGMENTATION AND REASSEMBLY CIRCUIT, 208 Pin, Plastic, QFP
IDT77V011L155DA 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
IDT77V011L155DA8 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
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