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參數(shù)資料
| 型號(hào)： | IDT72V51236L6BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 56/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLOW CTRL MULTI QUEUE 256-BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 多隊(duì)列流量控制 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（17x17） |
| 包裝： | 托盤 |
| 其它名稱： | 72V51236L6BB |
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9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
OW(1)
OutputWidth
LVTTL
This pin is setup during Master Reset and must not toggle during any device operation. This pin is used
INPUT
in conjunction with IW and BM to setup the data input and output bus widths to be a combination of x9,
x18 or x36, (providing that one port is x36).
PAE
Programmable
LVTTL
This pin provides the Almost-Empty flag status for the queue that has been selected on the output port
Almost-EmptyFlag
OUTPUT
for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
queue is almost-empty. This flag output may be duplicated on one of the
PAEn bus lines. This flag is
synchronized to RCLK.
PAEn/PRn
Programmable
LVTTL
On the 4Q device the
PAEn/ PRn bus is 4 bits wide. During a Master Reset this bus is setup for either
Almost-EmptyFlag
OUTPUT
Almost Empty mode or Packet mode. This output bus provides
PAE/ PRn status of all 4 queues, within
Bus/Packet Ready
a selected device. During Queue read/write operations these outputs provide programmable empty
Flag Bus
flagstatusorpacketreadystatus,ineitherdirectorpolledmode.Themodeofflagoperationisdetermined
during master reset via the state of the FM input. This flag bus is capable of High-Impedance state, this
is important during expansion of multi-queue devices. During direct operation the
PAEn/ PRn bus is
updated to show the
PAE/PRstatusofqueueswithinaselecteddevice.SelectionismadeusingRCLK,
ESTR and RDADD. During Polled operation the
PAEn/ PRn bus is loaded with the PAE/ PRn status
of multi-queue flow-control devices sequentially based on the rising edge of RCLK.
PAEorPRoperation
is determined by the state of PKT during master reset.
PAF
Programmable
LVTTL
This pin provides the Almost-Full flag status for the queue that has been selected on the input port for
Almost-FullFlag
OUTPUT
write operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected queue
is almost-full. This flag output may be duplicated on one of the
PAFnbuslines.Thisflagissynchronized
toWCLK.
PAFn
Programmable
LVTTL
On the 4Q device the
PAFnbusis4bitswide.ThisoutputbusprovidesPAFstatusofall4queues,within
Almost-Full Flag Bus
OUTPUT
a selected device. During Queue read/write operations these outputs provide programmable full flag
status, in either direct or polled mode. The mode of flag operation is determined during master reset
via the state of the FM input. This flag bus is capable of High-Impedance state, this is important during
expansion of multi-queue devices. During direct operation the
PAFn bus is updated to show the PAF
statusofaqueueswithinaselecteddevice.SelectionismadeusingWCLK,FSTR,WRADDandWADEN.
During Polled operation the
PAFnbusisloadedwiththePAFstatusofmulti-queueflow-controldevices
sequentially based on the rising edge of WCLK.
PKT(1)
Packet Mode
LVTTL
The state of this pin during a Master Reset will determine whether the part is operating in Packet mode
INPUT
providing both a Packet Ready (
PR) output and a Programmable Almost Empty (PAE) discrete output,
or standard mode, providing a (
PAE) output only. If this pin is HIGH during Master Reset the part will
operate in packet mode, if it is LOW then almost empty mode. If packet mode has been selected the read
port flag bus becomes packet ready flag bus,
PRn and the discrete packet ready flag, PR is functional.
If almost empty operation has been selected then the flag bus provides almost empty status,
PAEnand
thediscretealmostemptyflag,
PAEisfunctional,thePRflagisinactiveandshouldnotbeconnected.Packet
Ready utilizes user marked locations to identify start and end of packets being written into the device.
Packet Mode can only be selected if both the input port width and output port width are 36 bits.
PR
Packet Ready Flag
LVTTL
If packet mode has been selected this flag output provides Packet Ready status of the queue selected
for read operations. During a master reset the state of the PKT input determines whether Packet mode
of operation will be used. If Packet mode is selected, then the condition of the
PR flag andOV signalare
asserted indicates a packet is ready for reading. The user must mark the start of a packet and the end
of a packet when writing data into a queue. Using these Start Of Packet (SOP) and End Of Packet
(EOP) markers, the multi-queue device sets
PR LOW if one or more “complete” packets are available
in the queue. A complete packet(s) must be written before the user is allowed to switch queues.
PRS
PartialReset
LVTTL
APartialResetcanbeperformedonasinglequeueselectedwithinthemulti-queuedevice.BeforeaPartial
INPUT
Reset can be performed on a queue, that queue must be selected on both the write port and read port
2 clock cycles before the reset is performed. A Partial Reset is then performed by taking
PRS LOW for
one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to
the first memory location, none of the devices configuration will be changed.
PIN DESCRIPTIONS (CONTINUED)
Symbol
Name
I/O TYPE
Description
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| IDT72V51236L6BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51236L7-5BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51236L7-5BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51236L7-5BBI | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51243L6BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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