參數(shù)資料
型號(hào): IDT72V51236L6BB
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 41/56頁
文件大?。?/td> 0K
描述: IC FLOW CTRL MULTI QUEUE 256-BGA
標(biāo)準(zhǔn)包裝: 1
類型: 多隊(duì)列流量控制
安裝類型: 表面貼裝
封裝/外殼: 256-BBGA
供應(yīng)商設(shè)備封裝: 256-BGA(17x17)
包裝: 托盤
其它名稱: 72V51236L6BB
46
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WCLK
Dn
Prev
PAEn
RCLK
ESTR
RDADD
Device 5
101 xxx
100 011
D5Q3
tAH
tAS
tAH
tAS
1
tSKEW3
Previous value loaded on to PAE bus
1xxx
Device 5
2
RADEN
tQH
tQS
tSTH
tSTS
tPAE
5937 drw29
Device 5
PAE
tRAE
*AA*
*BB*
*CC*
*DD*
*FF*
*EE*
tRAE
D5 Qx Status
Bus
PAEn
Previous value loaded on to PAE bus
Device 5
tPAEHZ
tPAEZL
1xxx
REN
tENH
tENS
Device 5 -Qn
Wy
D5 Q3
Wy+1
D5 Q3
Wy+3
D5 Q3
Wy+2
D5 Q3
Wa+1
D5 Qn
tA
Wa
D5 Qx
tDH
tDS
WEN
WADEN
FSTR
tAH
100 11
tAS
WRADD
D5Q3
D3Q2
Wn
D5 Q3
Wn+1
D5Q3
Wx
D3 Q2
01110
Device 4
100 xx
*A*
*B*
*C*
*D*
*E*
*F*
tQH
tQS
tQH
tQS
tAH
tAS
tAH
tAS
tENS
tENH
tSTH
tSTS
Device 5
PAEn
1
2
tENS
tENH
Wp+1
Wp
Writes to Previous Q
tDH
tDS
tRAE
D5 Q3
status
1xxx
Device 5
1xxx
Figure 26.
PAEn - Direct Mode, Flag Operation – Devices in Expansion
Cycle:
*A*
Queue 3 of Device 5 is selected for write operations.
Word, Wp is written into the previously selected queue.
*AA* Queue 3 of Device 5 is selected for read operations.
Another device has control of the
PAEn bus.
The discrete
PAE output of device 5 is currently in High-Impedance and the PAE active flag is controlled by the previously selected device.
*B*
Word Wp+1 is written into the previously selected queue.
*BB* Word, Wa+1 is read from Qx of D5, due to FWFT operation.
*C*
Word, Wn is written into the newly selected queue, Q3 of D5. This write will cause the
PAE flag on the read port to go from LOW to HIGH (not almost empty) after time,
tSKEW3 + RCLK + tRAE (if tSKEW3 is violated one extra RCLK cycle will be added.
*CC* Word, Wy from the newly selected queue, Q3 will be read out due to FWFT operation.
Device 5 is selected on the
PAEn bus. Q3 of device 5 will therefore have is PAE status output on PAE[3]. There is a single RCLK cycle latency before the PAEn bus changes
to the new selection.
*D*
Queue 2 of Device 3 is selected for write operations.
Word Wn+1 is written into Q3 of D5.
*DD* The
PAEn bus changes control to D5, the PAEn outputs of D5 go to Low-Impedance and are placed onto the outputs. The previously selected device now places its
PAEn outputs into High-Impedance to prevent bus contention. Word, Wy+1 is read from Q3 of D5.
The discrete
PAE flag will go HIGH to show that Q3 of D5 is not almost empty. Q3 of device 5 will have its PAE status output on PAE[3].
*E*
No writes occur.
*EE* Word, Wy+2 is read from Q3 of D5.
*F*
Device 4 is selected on the write port for the
PAFn bus.
Word, Wx is written into Q2 of D3.
*FF* The
PAEn bus updates to show that Q3 of D5 is almost empty based on the reading out of word, Wy+1.
The discrete
PAE flag goes LOW to show that Q3 of D5 is almost empty based on the reading of Wy+1.
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