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參數(shù)資料
| 型號： | IDT72V2113L7-5PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SUPERSYNCII 7-5NS 80TQFP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲容量： | 4.7Mb（262k x 18） |
| 訪問時間： | 5ns |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72V2113L7-5PF8 |
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IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
JUNE 1, 2010
PROGRAMMING FLAG OFFSETS
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72V2103/
72V2113 has internal registers for these offsets. There are eight default offset
valuesselectableduringMasterReset.TheseoffsetvaluesareshowninTable
2.OffsetvaluescanalsobeprogrammedintotheFIFOinoneoftwoways;serial
or parallel loading method. The selection of the loading method is done using
the
LD (Load) pin. During Master Reset, the state of the LD input determines
whether serial or parallel flag offset programming is enabled. A HIGH on
LD
duringMasterResetselectsserialloadingofoffsetvalues.ALOWon
LDduring
Master Reset selects parallel loading of offset values.
In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q0-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.
IDT72V2103, IDT72V2113
LD
FSEL0
FSEL1
Offsets n,m
L
H
16,383
L
H
L
8,191
L
H
4,095
H
L
H
2,047
H
L
1,023
HH
L
511
H
255
L
127
LD
FSEL0
FSEL1
Program Mode
H
X
Serial(3)
L
X
Parallel(4)
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for
PAE.
2. m = full offset for
PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
Figure 3, Programmable Flag Offset Programming Sequence, summaries
thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes.
For a more detailed description, see discussion that follows.
Theoffsetregistersmaybeprogrammed(andreprogrammed)anytimeafter
Master Reset, regardless of whether serial or parallel programming has been
selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72V2103/72V2113 can be configured during the Master Reset
cycle with either synchronous or asynchronous timing for
PAFandPAEflags
by use of the PFM pin.
If synchronous
PAF/PAE configuration is selected (PFM, HIGH during
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly,
PAEisassertedandupdatedontherisingedgeofRCLK
only and not WCLK. For detail timing diagrams, see Figure 18 for synchronous
PAF timing and Figure 19 for synchronous PAE timing.
If asynchronous
PAF/PAE configuration is selected (PFM, LOW during
MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK.Similarly,PAE
isassertedLOWontheLOW-to-HIGHtransitionofRCLK.
PAEisresettoHIGH
ontheLOW-to-HIGHtransitionofWCLK.Fordetailtimingdiagrams,seeFigure
20 for asynchronous
PAFtimingandFigure21forasynchronousPAEtiming.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72V2113L7-5PFGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SUPERSYNCII 6NS 80TQFP |
| IDT72V211L10J | 功能描述:IC FIFO SYNC 512X9 10NS 32-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72V211L10J8 | 功能描述:IC FIFO SYNC 512X9 10NS 32-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72V211L10PF | 功能描述:IC FIFO SYNC 512X9 10NS 32-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72V211L10PF8 | 功能描述:IC FIFO SYNC 512X9 10NS 32-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
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