IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
參數(shù)資料
型號: IDT72V2113L7-5PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 33/46頁
文件大小: 0K
描述: IC FIFO SUPERSYNCII 7-5NS 80TQFP
標(biāo)準(zhǔn)包裝: 750
系列: 72V
功能: 同步
存儲容量: 4.7Mb(262k x 18)
訪問時間: 5ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72V2113L7-5PF8
39
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
JUNE 1, 2010
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one
device. The exceptions are the
EF and FF functions in IDT Standard mode
and the
IR and OR functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for
EF/FF deassertion and IR/OR
assertion to vary by one cycle between FIFOs. In IDT Standard mode, such
problems can be avoided by creating composite flags, that is, ANDing
EF
Figure 29. Block Diagram of Width Expansion
For the x18 Input or x18 Output bus Width: 131,072 x 36 and 262,144 x 36
For both x9 Input and x9 Output bus Widths: 262,144 x 18 and 524,288 x 18
WRITE CLOCK (WCLK)
m + n
m
n
MASTER RESET (MRS)
READ CLOCK (RCLK)
DATA
OUT
n
m + n
WRITE ENABLE (WEN)
FULL FLAG/INPUT READY (FF/IR) #1
PROGRAMMABLE (PAF)
PROGRAMMABLE (PAE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
OUTPUT ENABLE (OE)
READ ENABLE (REN)
m
LOAD (LD)
IDT
72V2103
72V2113
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PARTIAL RESET (PRS)
IDT
72V2103
72V2113
6119 drw32
FULL FLAG/INPUT READY (FF/IR) #2
HALF-FULL FLAG (HF)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
FIFO
#2
GATE
(1
)
GATE
(1
)
D0 - Dm
DATA IN
Dm+1 - Dn
Q0 - Qm
Qm+1 - Qn
FIFO
#1
of every FIFO, and separately ANDing
FF of every FIFO. In FWFT mode,
composite flags can be created by ORing
OR of every FIFO, and separately
ORing
IR of every FIFO.
Figure 29 demonstrates a width expansion using two IDT72V2103/
72V2113devices.Ifx18Inputorx18OutputbusWidthisselected,D0-D17 from
each device form a 36-bit wide input bus and Q0-Q17 from each device form
a36-bitwideoutputbus.Ifbothx9Inputandx9OutputbusWidthsareselected,
D0-D8 from each device form an 18-bit wide input bus and Q0-Q8 from each
deviceforman18-bitwideoutputbus.Anywordwidthcanbeattainedbyadding
additional IDT72V2103/72V2113 devices.
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